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Hi! tsutsui-san,


From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
Date: Sun, 24 Sep 2006 09:52:10 +0900

> kiyohara@kk.iij4u.or.jp wrote:
> 
> > I think serious dangerous for initialization of MIPS timer.  My Cobalt
> > Qube panic() in hardclock().  It reason for hardclock() is called before
> > softclock is initialized. 
> 
> Yes, it could happen on my RaQ2 while it would be some timing dependent.
> 
> Maybe we should move _splnone() from autoconf.c:cpu_configure() to
> mips/mips3_clockintr():cpu_initclocks(), but I wonder
> we should still enable other interrupts than INT5 in
> cpu_configure() or not. (since initclocks() is called
> right after cpu_configure() in subr_autoconf.c).

All right.  Please check. ;-)

For which port do you need it?

Thanks,
--
kiyohara


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Index: arch/cobalt/cobalt/autoconf.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/cobalt/autoconf.c,v
retrieving revision 1.23
diff -u -r1.23 autoconf.c
--- arch/cobalt/cobalt/autoconf.c	10 Sep 2006 06:41:09 -0000	1.23
+++ arch/cobalt/cobalt/autoconf.c	26 Sep 2006 17:28:33 -0000
@@ -55,8 +55,11 @@
 	if (config_rootfound("mainbus", NULL) == NULL)
 		panic("no mainbus found");
 
-	/* enable all interrupts */
-	_splnone();
+	/*
+	 * Enable interrupts excluding clock, because initclock() not call
+	 * yet.
+	 */
+	_splnoclock();
 }
 
 void
Index: arch/cobalt/include/intr.h
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/include/intr.h,v
retrieving revision 1.23
diff -u -r1.23 intr.h
--- arch/cobalt/include/intr.h	7 Sep 2006 03:38:55 -0000	1.23
+++ arch/cobalt/include/intr.h	26 Sep 2006 17:28:33 -0000
@@ -72,6 +72,7 @@
 void _splnone(void);
 void _setsoftintr(int);
 void _clrsoftintr(int);
+void _splnoclock(void);
 
 #define splhigh()       _splraise(MIPS_INT_MASK)
 #define spl0()          (void)_spllower(0)
Index: arch/mips/mips/locore.S
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/locore.S,v
retrieving revision 1.162
diff -u -r1.162 locore.S
--- arch/mips/mips/locore.S	7 Sep 2006 02:40:31 -0000	1.162
+++ arch/mips/mips/locore.S	26 Sep 2006 17:28:46 -0000
@@ -756,6 +756,18 @@
 	nop
 END(_splnone)
 
+LEAF(_splnoclock)
+	mtc0	zero, MIPS_COP_0_CAUSE		# clear SOFT_INT bits
+	COP0_SYNC
+	li	v0, ((MIPS_INT_MASK & ~MIPS_INT_MASK_5)| MIPS_SR_INT_IE)
+	DYNAMIC_STATUS_MASK(v0,t0)		# machine dependent masking
+	mtc0	v0, MIPS_COP_0_STATUS		# enable all sources
+	COP0_SYNC
+	nop
+	j	ra
+	nop
+END(_splnoclock)
+
 /*
  * u_int32_t mips_cp0_cause_read(void)
  *
Index: arch/mips/mips/mips3_clockintr.c
===================================================================
RCS file: /cvsroot/src/sys/arch/mips/mips/mips3_clockintr.c,v
retrieving revision 1.2
diff -u -r1.2 mips3_clockintr.c
--- arch/mips/mips/mips3_clockintr.c	10 Sep 2006 14:27:38 -0000	1.2
+++ arch/mips/mips/mips3_clockintr.c	26 Sep 2006 17:28:46 -0000
@@ -144,6 +144,9 @@
 #ifdef	__HAVE_TIMECOUNTER
 	mips3_init_tc();
 #endif
+
+	/* enable all interrupts */
+	_splnone();
 }
 
 /*

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