Izumi

Your kernel works here fine:

NetBSD 3.99.17 (GENERIC) #60: Sun Apr  9 16:38:43 JST 2006
         tsutsui@mirage:/usr/src/sys/arch/cobalt/compile/GENERIC
Cobalt Qube 2
total memory =3D 128 MB
avail memory =3D 121 MB
mainbus0 (root)
com0 at mainbus0 addr 0x1c800000 level 3: st16650a, working fifo
com0: console
cpu0 at mainbus0: QED RM5200 CPU (0x28a0) Rev. 10.0 with built-in FPU =20
Rev. 10.0
cpu0: 32KB/32B 2-way set-associative L1 Instruction cache, 48 TLB entries
cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache

But the second version of the USB kernel does also not boot, same like =20
the first version.

Thanks for your work

Andreas


Quoting Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>:

> Hi,
>
> I'd also like to commit the attached diff which enable
> to identify cobalt models (Qube2700/Cube2/RaQ/RaQ2), and
> I've also put GENERIC kernel (which also includes the previous
> todclock device changes) at:
> http://www.ceres.dti.ne.jp/~tsutsui/netbsd/netbsd-cobalt-GENERIC-20060409.=
gz
>
> The device info is taken from Linux sources and it works
> fine on my RaQ2:
> ---
> Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,  =20
> 2005, 2006
>     The NetBSD Foundation, Inc.  All rights reserved.
> Copyright (c) 1982, 1986, 1989, 1991, 1993
>     The Regents of the University of California.  All rights reserved.
>
> NetBSD 3.99.17 (COLT) #193: Sun Apr  9 10:10:05 JST 2006
>         tsutsui@mirage:/usr/src/sys/arch/cobalt/compile/COLT
> Cobalt RaQ 2
> total memory =3D 256 MB
> avail memory =3D 247 MB
> mainbus0 (root)
> com0 at mainbus0 addr 0x1c800000 level 3: st16650a, working fifo
> com0: console
> cpu0 at mainbus0: QED RM5200 CPU (0x28a0) Rev. 10.0 with built-in  =20
> FPU Rev. 10.0
> cpu0: 32KB/32B 2-way set-associative L1 Instruction cache, 48 TLB entries
> cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache
> mcclock0 at mainbus0 addr 0x10000070: mc146818 compatible time-of-day cloc=
k
> panel0 at mainbus0 addr 0x1f000000
>  :
> ---
> but any reports on other medels would be appreciated.
>
> ---
> Izumi Tsutsui
>
>
> Index: cobalt/machdep.c
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> RCS file: /cvsroot/src/sys/arch/cobalt/cobalt/machdep.c,v
> retrieving revision 1.59
> diff -u -r1.59 machdep.c
> --- cobalt/machdep.c=099 Apr 2006 01:29:38 -0000=091.59
> +++ cobalt/machdep.c=099 Apr 2006 06:48:32 -0000
> @@ -104,6 +104,18 @@
>  int=09bootunit =3D -1;
>  int=09bootpart =3D -1;
>
> +u_int cobalt_id;
> +static const char * const cobalt_model[] =3D
> +{
> +=09NULL,
> +=09NULL,
> +=09NULL,
> +=09"Cobalt Qube 2700",
> +=09"Cobalt RaQ",
> +=09"Cobalt Qube 2",
> +=09"Cobalt RaQ 2"
> +};
> +#define COBALT_MODELS=09(sizeof(cobalt_model) / sizeof(cobalt_model[0]))
>
>  phys_ram_seg_t mem_clusters[VM_PHYSSEG_MAX];
>  int mem_cluster_cnt;
> @@ -111,6 +123,7 @@
>  void=09mach_init(unsigned int, u_int, char*);
>  void=09decode_bootstring(void);
>  static char *=09strtok_light(char *, const char);
> +static u_int read_board_id(void);
>
>  /*
>   * safepri is a safe priority for sleep to set for a spin-wait during
> @@ -181,6 +194,13 @@
>  =09}
>  #endif
>
> +=09cobalt_id =3D read_board_id();
> +=09if (cobalt_id >=3D COBALT_MODELS || cobalt_model[cobalt_id] =3D=3D NUL=
L)
> +=09=09sprintf(cpu_model, "Cobalt unknown model (board ID %u)",
> +=09=09    cobalt_id);
> +=09else
> +=09=09strcpy(cpu_model, cobalt_model[cobalt_id]);
> +
>  =09physmem =3D btoc(memsize - MIPS_KSEG0_START);
>
>  =09consinit();
> @@ -227,8 +247,6 @@
>  =09=09kgdb_connect(0);
>  #endif
>
> -=09strcpy(cpu_model, "Cobalt Microserver");
> -
>  =09/*
>  =09 * Load the rest of the available pages into the VM system.
>  =09 */
> @@ -267,6 +285,7 @@
>  =09 * Good {morning,afternoon,evening,night}.
>  =09 */
>  =09printf("%s%s", copyright, version);
> +=09printf("%s\n", cpu_model);
>  =09format_bytes(pbuf, sizeof(pbuf), ctob(physmem));
>  =09printf("total memory =3D %s\n", pbuf);
>
> @@ -561,3 +580,34 @@
>
>  =09return NULL;
>  }
> +
> +/*
> + * Get board ID of cobalt models.
> + *
> + * The board ID info is stored at the PCI config register
> + * on the PCI-ISA bridge part of the VIA VT82C586 chipset.
> + * We can't use pci_conf_read(9) yet here, so read it directly.
> + */
> +static u_int
> +read_board_id(void)
> +{
> +=09volatile uint32_t *pcicfg_addr, *pcicfg_data;
> +=09uint32_t reg;
> +
> +#define PCIB_PCI_BUS=09=090
> +#define PCIB_PCI_DEV=09=099
> +#define PCIB_PCI_FUNC=09=090
> +#define PCIB_BOARD_ID_REG=090x94
> +#define COBALT_BOARD_ID(reg)=09((reg & 0x000000f0) >> 4)
> +
> +=09pcicfg_addr =3D (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_PCICFG_ADD=
R);
> +=09pcicfg_data =3D (uint32_t *)MIPS_PHYS_TO_KSEG1(GT_BASE + GT_PCICFG_DAT=
A);
> +
> +=09*pcicfg_addr =3D PCICFG_ENABLE |
> +=09    (PCIB_PCI_BUS << 16) | (PCIB_PCI_DEV << 11) | (PCIB_PCI_FUNC << 8)=
 |
> +=09    PCIB_BOARD_ID_REG;
> +=09reg =3D *pcicfg_data;
> +=09*pcicfg_addr =3D 0;
> +
> +=09return COBALT_BOARD_ID(reg);
> +}
> Index: include/cpu.h
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> RCS file: /cvsroot/src/sys/arch/cobalt/include/cpu.h,v
> retrieving revision 1.10
> diff -u -r1.10 cpu.h
> --- include/cpu.h=094 Sep 2001 06:23:16 -0000=091.10
> +++ include/cpu.h=099 Apr 2006 06:48:32 -0000
> @@ -1,3 +1,20 @@
>  /*=09$NetBSD: cpu.h,v 1.10 2001/09/04 06:23:16 simonb Exp $=09*/
>
> +#ifndef _COBALT_CPU_H_
> +#define _COBALT_CPU_H_
> +
>  #include <mips/cpu.h>
> +
> +#ifdef _KERNEL
> +#ifndef _LOCORE
> +extern u_int cobalt_id;
> +
> +#define COBALT_ID_QUBE2700=093
> +#define COBALT_ID_RAQ=09=094
> +#define COBALT_ID_QUBE2=09=095
> +#define COBALT_ID_RAQ2=09=096
> +
> +#endif /* !_LOCORE */
> +#endif /* _KERNEL */
> +
> +#endif /* !_COBALT_CPU_H_ */
>