Subject: Re: Netbsd 3.0 Crash on file transfert
To: None <thierry.rangeard@gmail.com>
From: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
List: port-cobalt
Date: 03/18/2006 03:59:36
In article <2ED67911-5DC9-47F4-BCE5-E9D88F67F199@gmail.com>
thierry.rangeard@gmail.com wrote:

> The only thing that I could mentioned, but I don't know if it's  
> linked  the swap is never used or deacreasing during this load.

I don't think so. The swap is only used if ~all RAM is ran out.
Actually swap is used on my RaQ2 (with 256MB RAM) when I tried
"make -j 30" in sys/arch/cobalt/compile/GENERIC:
---
% top -n 10
load averages: 29.92, 18.00,  8.83    up 0 days,  1:13    up 0 days,  1:13   03:45:40
120 processes: 30 runnable, 89 sleeping, 1 on processor
CPU states:     % user,     % nice,     % system,     % interrupt,     % idle
Memory: 152M Act, 74M Inact, 9216K Wired, 11M Exec, 51M File, 824K Free
Swap: 128M Total, 3508K Used, 125M Free

  PID USERNAME PRI NICE   SIZE   RES STATE      TIME   WCPU    CPU COMMAND
  794 tsutsui   62    0  5992K 9180K RUN        0:08  3.71%  3.71% cc1
  311 tsutsui   60    0  6580K   10M RUN        0:08  3.56%  3.56% cc1
  816 tsutsui   61    0  6496K 9480K RUN        0:05  3.47%  3.47% cc1
  548 tsutsui   62    0  6228K   11M RUN        0:09  3.37%  3.37% cc1
  608 tsutsui   61    0  6568K 9916K RUN        0:05  3.23%  3.22% cc1
  802 tsutsui   61    0  6324K 9764K RUN        0:05  3.18%  3.17% cc1
  323 tsutsui   61    0  6396K 9716K RUN        0:04  3.13%  3.12% cc1
 1397 tsutsui   60    0  6068K 7308K RUN        0:03  3.15%  3.12% cc1
  274 tsutsui   61    0  5792K 9024K RUN        0:09  3.03%  3.03% cc1
  690 tsutsui   60    0  6628K   11M RUN        0:08  3.03%  3.03% cc1

% 
---
Maybe your cobalt has enough RAM for your jobs?

> Does it happen with all kernel branch or it's specific to the 3.0 ?.

"TLB miss on cache flush" panic still happens with -current
(updated around 20060314) at least on my RaQ2.

> Sorry I would like to be more involved but I m not a C developer what  
> exactly do your patch ?

I guess you could look at some MIPS manuals (not C manual),
but in short words, the "index" cache ops never cause TLB miss
but may flush extra data.
(though TLB miss should not happen in this case anyway)

> I can also make the test with a 3 com PCI, I have to check if it's  
> supported by the kernel.

ex(4) should work since it works on my NetBSD/arc (mipsel) machine,
but you have to uncomment "ex* at pci? .." line in your kernel config.
---
Izumi Tsutsui