On 11/9/05, Andy Ruhl <acruhl@gmail.com> wrote:
> On 11/9/05, Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> wrote:
> > In article <78a2305a0511090650j1a268a17o16d7df142e0cec6@mail.gmail.com>
> > acruhl@gmail.com wrote:
> >
> > > > > Does the -current kernel have the same problem?
> > > > > ftp://ftp.netbsd.org/pub/NetBSD-daily/HEAD/
> > > > I will try this Izumi.
> > > Ok. The first test, which is doing ftp, did not crash the machine.
> > > I'll see if I can run this kernel for a while and see what happens.
> >
> > Ok, thanks.
> >
> > > Is this a known fix that can be applied to release-3?
> > > I can test if so.
> >
> > Could you please try the attached patch for netbsd-3?
> > I'll send a pullup request if it actually fixes your problem.
> > ---
> > Izumi Tsutsui
> >
> >
> > Index: sys/arch/mips/include/cache.h
> > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > RCS file: /cvsroot/src/sys/arch/mips/include/cache.h,v
> > retrieving revision 1.7
> > diff -u -r1.7 cache.h
> > --- sys/arch/mips/include/cache.h       1 Mar 2005 04:23:44 -0000      =
 1.7
> > +++ sys/arch/mips/include/cache.h       9 Nov 2005 14:59:26 -0000
> > @@ -185,8 +185,6 @@
> >
> >  extern int mips_scache_unified;
> >
> > -extern u_int mips_sdcache_forceinv;    /* force pmap to invalidate for=
 r5ksc */
> > -
> >  /* TERTIARY CACHE VARIABLES */
> >  extern u_int mips_tcache_size;         /* always unified */
> >  extern u_int mips_tcache_line_size;
> > @@ -201,6 +199,8 @@
> >  extern u_int mips_cache_alias_mask;
> >  extern u_int mips_cache_prefer_mask;
> >
> > +extern int mips_cache_virtual_alias;
> > +
> >  /*
> >   * XXX XXX XXX THIS SHOULD NOT EXIST XXX XXX XXX
> >   */
> > Index: sys/arch/mips/include/pmap.h
> > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > RCS file: /cvsroot/src/sys/arch/mips/include/pmap.h,v
> > retrieving revision 1.46
> > diff -u -r1.46 pmap.h
> > --- sys/arch/mips/include/pmap.h        17 Jan 2005 04:54:14 -0000     =
 1.46
> > +++ sys/arch/mips/include/pmap.h        9 Nov 2005 14:59:26 -0000
> > @@ -180,8 +180,10 @@
> >  /*
> >   * Alternate mapping hooks for pool pages.  Avoids thrashing the TLB.
> >   */
> > -#define        PMAP_MAP_POOLPAGE(pa)   MIPS_PHYS_TO_KSEG0((pa))
> > -#define        PMAP_UNMAP_POOLPAGE(va) MIPS_KSEG0_TO_PHYS((va))
> > +vaddr_t mips_pmap_map_poolpage(paddr_t);
> > +paddr_t mips_pmap_unmap_poolpage(vaddr_t);
> > +#define        PMAP_MAP_POOLPAGE(pa)   mips_pmap_map_poolpage(pa)
> > +#define        PMAP_UNMAP_POOLPAGE(va) mips_pmap_unmap_poolpage(va)
> >
> >  /*
> >   * Other hooks for the pool allocator.
> > Index: sys/arch/mips/mips/cache.c
> > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > RCS file: /cvsroot/src/sys/arch/mips/mips/cache.c,v
> > retrieving revision 1.26
> > diff -u -r1.26 cache.c
> > --- sys/arch/mips/mips/cache.c  1 Mar 2005 04:23:44 -0000       1.26
> > +++ sys/arch/mips/mips/cache.c  9 Nov 2005 14:59:26 -0000
> > @@ -129,8 +129,6 @@
> >
> >  int mips_scache_unified;
> >
> > -u_int mips_sdcache_forceinv =3D 0;
> > -
> >  /* TERTIARY CACHE VARIABLES */
> >  u_int mips_tcache_size;                /* always unified */
> >  u_int mips_tcache_line_size;
> > @@ -154,6 +152,8 @@
> >  u_int mips_cache_alias_mask;   /* for virtually-indexed caches */
> >  u_int mips_cache_prefer_mask;
> >
> > +int mips_cache_virtual_alias;
> > +
> >  struct mips_cache_ops mips_cache_ops;
> >
> >  #ifdef MIPS1
> > @@ -421,6 +421,11 @@
> >
> >                 mips3_get_cache_config(csizebase);
> >
> > +               if (mips_picache_size > PAGE_SIZE ||
> > +                   mips_pdcache_size > PAGE_SIZE)
> > +                       /* no VCE support if there is no L2 cache */
> > +                       mips_cache_virtual_alias =3D 1;
> > +
> >                 switch (mips_picache_line_size) {
> >                 case 16:
> >                         mips_cache_ops.mco_icache_sync_all =3D
> > @@ -494,6 +499,10 @@
> >
> >                 mips3_get_cache_config(csizebase);
> >
> > +               if (mips_picache_size > PAGE_SIZE ||
> > +                   mips_pdcache_size > PAGE_SIZE)
> > +                       mips_cache_virtual_alias =3D 1;
> > +
> >                 switch (mips_picache_line_size) {
> >                 case 32:
> >                         mips_cache_ops.mco_icache_sync_all =3D
> > @@ -590,6 +599,7 @@
> >                     ~(PAGE_SIZE - 1);
> >                 mips_cache_prefer_mask =3D
> >                     max(mips_pdcache_size, mips_picache_size) - 1;
> > +               mips_cache_virtual_alias =3D 1;
> >                 /* cache ops */
> >                 mips_cache_ops.mco_icache_sync_all =3D
> >                     r5900_icache_sync_all_64;
> > @@ -619,6 +629,8 @@
> >
> >                 mips4_get_cache_config(csizebase);
> >
> > +               /* VCE is handled by hardware */
> > +
> >                 mips_cache_ops.mco_icache_sync_all =3D
> >                     r10k_icache_sync_all;
> >                 mips_cache_ops.mco_icache_sync_range =3D
> > @@ -670,13 +682,27 @@
> >  #if defined(MIPS3) || defined(MIPS4)
> >         case MIPS_R4000:
> >                 /*
> > -                * R4000/R4400 always detects virtual alias as if
> > -                * primary cache size is 32KB. Actual primary cache siz=
e
> > -                * is ignored wrt VCED/VCEI.
> > +                * R4000/R4400 detects virtual alias by VCE as if
> > +                * its primary cache size were 32KB, because it always
> > +                * compares 3 bits of vaddr[14:12] which causes
> > +                * primary cache miss and PIdx[2:0] in the secondary
> > +                * cache tag regardless of its primary cache size.
> > +                * i.e. VCE could happen even if there is no actual
> > +                * virtual alias on its 8KB or 16KB primary cache
> > +                * which has only 1 or 2 bit valid PIdx in 4KB page.
> > +                * Actual primary cache size is ignored wrt VCE
> > +                * and virtual aliases are resolved by the VCE hander,
> > +                * but it's still worth to avoid unnecessary VCE by
> > +                * setting alias mask and prefer mask to 32K, though
> > +                * some other possible aliases (maybe caused by KSEG0
> > +                * accesses which can't be managed by PMAP_PREFER(9))
> > +                * will still be resolved by the VCED/VCEI handler.
> >                  */
> >                 mips_cache_alias_mask =3D
> > -                       (MIPS3_MAX_PCACHE_SIZE - 1) & ~(PAGE_SIZE - 1);
> > +                   (MIPS3_MAX_PCACHE_SIZE - 1) & ~PAGE_MASK;   /* va[1=
4:12] */
> >                 mips_cache_prefer_mask =3D MIPS3_MAX_PCACHE_SIZE - 1;
> > +
> > +               mips_cache_virtual_alias =3D 0;
> >                 /* FALLTHROUGH */
> >         case MIPS_R4600:
> >  #ifdef ENABLE_MIPS_R4700
> > Index: sys/arch/mips/mips/mem.c
> > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > RCS file: /cvsroot/src/sys/arch/mips/mips/mem.c,v
> > retrieving revision 1.29
> > diff -u -r1.29 mem.c
> > --- sys/arch/mips/mips/mem.c    7 Aug 2003 16:28:33 -0000       1.29
> > +++ sys/arch/mips/mips/mem.c    9 Nov 2005 14:59:27 -0000
> > @@ -76,6 +76,9 @@
> >   * Memory special file
> >   */
> >
> > +#include "opt_cputype.h"
> > +#include "opt_mips_cache.h"
> > +
> >  #include <sys/cdefs.h>
> >  __KERNEL_RCSID(0, "$NetBSD: mem.c,v 1.29 2003/08/07 16:28:33 agc Exp $=
");
> >
> > @@ -89,6 +92,8 @@
> >
> >  #include <machine/cpu.h>
> >
> > +#include <mips/cache.h>
> > +
> >  #include <uvm/uvm_extern.h>
> >
> >  extern paddr_t avail_end;
> > @@ -142,6 +147,10 @@
> >                                 return (EFAULT);
> >                         v +=3D MIPS_KSEG0_START;
> >                         error =3D uiomove((void *)v, c, uio);
> > +#if defined(MIPS3_PLUS)
> > +                       if (mips_cache_virtual_alias)
> > +                               mips_dcache_wbinv_range(v, c);
> > +#endif
> >                         continue;
> >
> >                 case DEV_KMEM:
> > @@ -156,6 +165,10 @@
> >                             uio->uio_rw =3D=3D UIO_READ ? B_READ : B_WR=
ITE)))
> >                                 return (EFAULT);
> >                         error =3D uiomove((void *)v, c, uio);
> > +#if defined(MIPS3_PLUS)
> > +                       if (mips_cache_virtual_alias)
> > +                               mips_dcache_wbinv_range(v, c);
> > +#endif
> >                         continue;
> >
> >                 case DEV_NULL:
> > Index: sys/arch/mips/mips/pmap.c
> > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > RCS file: /cvsroot/src/sys/arch/mips/mips/pmap.c,v
> > retrieving revision 1.157
> > diff -u -r1.157 pmap.c
> > --- sys/arch/mips/mips/pmap.c   1 Mar 2005 04:23:44 -0000       1.157
> > +++ sys/arch/mips/mips/pmap.c   9 Nov 2005 14:59:27 -0000
> > @@ -641,10 +641,10 @@
> >                          * were being accessed by KSEG0 (cached) addres=
ses and
> >                          * may cause cache coherency problems when the =
page
> >                          * is reused with KSEG2 (mapped) addresses.  Th=
is may
> > -                        * cause problems on machines without secondary=
 caches.
> > +                        * cause problems on machines without VCED/VCEI=