On Mon, 12 Jul 2004, Andy Ruhl wrote:

> o The onboard IDE controller wants to use Ultra/33. No problem there.
> I'm just wondering if it's going to support my 250 gig drive. If not,
> I'll probably be using another controller in the PCI slot as well.

From what I heard it will.

> o I assume lcd0 is the lcd panel after grepping the code. Cool. I
> could write a script to change the lcd to read "bite me" when the load
> average goes over 3 or something...

thereby increasing the load ;)

> o Not sure what gt is.

It's a pci bridge.

> o USB? Looks like it might not be supported but that would be cool. Is
> there some USB header stuff on the motherboard somewhere? It would be
> cool to have USB on this thing because that would expand it's
> possibilities greatly.

I don't know. I looked for a USB socket on my mainboard but couldn't find 
it. Since the serial port in my raq2 isn't attached, I thought this was 
maybe it but this probably isn't true because Pete's dmesg does have a 
com0.

> Anyone have a dmesg from 2.0-something?

This is from a cobalt raq2. (Looks very similar to the dmesg you posted)

##### help == NULL
Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
     The NetBSD Foundation, Inc.  All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
     The Regents of the University of California.  All rights reserved.

NetBSD 2.0_BETA (DRAGONFIRE) #0: Sun Jul  4 19:34:35 CEST 2004
 	root@okuma.amelgem.be:/usr/build/netbsd-2-0/obj/cobalt/sys/arch/cobalt/compile/DRAGONFIRE
total memory = 128 MB
avail memory = 122 MB
mainbus0 (root)
cpu0 at mainbus0: QED RM5200 CPU (0x28a0) Rev. 10.0 with built-in FPU Rev. 10.0
cpu0: 32KB/32B 2-way set-associative L1 Instruction cache, 48 TLB entries
cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache
panel0 at mainbus0 addr 0x1f000000
gt0 at mainbus0 addr 0x14000000
pci0 at gt0
pci0: i/o space, memory space enabled, rd/line, wr/inv ok
pchb0 at pci0 dev 0 function 0: Galileo GT-64111 System Controller, rev 1
tlp0 at pci0 dev 7 function 0: DECchip 21143 Ethernet, pass 4.1
tlp0: interrupting at level 1
tlp0: Ethernet address 00:10:e0:00:81:8b
lxtphy0 at tlp0 phy 1: LXT970 10/100 media interface, rev. 3
lxtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
vendor 0x1000 product 0x0006 (SCSI mass storage, revision 0x02) at pci0 dev 8 function 0 not configured
pcib0 at pci0 dev 9 function 0
pcib0: vendor 0x1106 product 0x0586, rev 39
viaide0 at pci0 dev 9 function 1
viaide0: VIA Technologies VT82C586 (Apollo VP) ATA33 controller
viaide0: bus-master DMA support present
viaide0: primary channel configured to compatibility mode
viaide0: primary channel interrupting at irq 14
atabus0 at viaide0 channel 0
viaide0: secondary channel configured to compatibility mode
viaide0: secondary channel interrupting at irq 15
atabus1 at viaide0 channel 1
vendor 0x1106 product 0x3038 (USB serial bus, revision 0x02) at pci0 dev 9 function 2 not configured
tlp1 at pci0 dev 12 function 0: DECchip 21143 Ethernet, pass 4.1
tlp1: interrupting at level 2
tlp1: Ethernet address 00:10:e0:00:81:7d
lxtphy1 at tlp1 phy 1: LXT970 10/100 media interface, rev. 3
lxtphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
IPsec: Initialized Security Association Processing.
wd0 at atabus0 drive 0: <Maxtor 6E040L0>
wd0: drive supports 16-sector PIO transfers, LBA addressing
wd0: 39205 MB, 79656 cyl, 16 head, 63 sec, 512 bytes/sect x 80293248 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
wd0(viaide0:0:0): using PIO mode 4, Ultra-DMA mode 2 (Ultra/33) (using DMA data transfers)
boot device: wd0
root on wd0a dumps on wd0b

kind regards,
Dieter

>
> Thanks!
>
> Andy
>

-- 

 	There is virtue in doing the right thing just for
 	the sake of doing it right.  -- Nicholas Petreley