Subject: fwohci working on the Qube 2J
To: None <port-cobalt@NetBSD.org>
From: KIYOHARA Takashi <kiyohara@kk.iij4u.or.jp>
List: port-cobalt
Date: 02/13/2004 22:51:19
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Hi all.
PCI card fwohci working. However, a speed of operation is very slow.
Only 1Mbyte comes out. I think that it is the problem of the processing
speed of CPU.
magician# uname -a
NetBSD magician.fool 1.6ZH NetBSD 1.6ZH (MAGICIAN) #0: Fri Feb 13 02:40:04 JST 2004 lance@highpriestess.fool:/usr/src/sys/arch/cobalt/compile/MAGICIAN cobalt
dd(1) operation
---------------
magician# mount /dev/sd0e /mnt
magician# cd /mnt
magician# dd if=/dev/zero of=dd.test count=20480
20480+0 records in
20480+0 records out
10485760 bytes transferred in 9.613 secs (1090789 bytes/sec)
The result of iostat at that time
---------------------------------
magician# iostat -w 2
tty wd0 sd0 cpu
tin tout KB/t t/s MB/s KB/t t/s MB/s us ni sy in id
0 12 6.13 0 0.00 4.38 0 0.00 0 0 2 0 98
0 93 0.00 0 0.00 34.17 6 0.20 3 0 19 0 78 <-- dd begin
0 31 0.00 0 0.00 64.00 16 1.03 8 0 92 0 0
0 31 0.00 0 0.00 64.00 17 1.06 12 0 88 0 0
0 31 0.00 0 0.00 64.00 17 1.06 10 0 90 0 0
0 31 8.00 1 0.00 62.35 17 1.03 8 0 92 0 0
0 87 0.00 0 0.00 64.00 10 0.62 7 0 51 0 41 <-- dd end
0 31 0.00 0 0.00 0.00 0 0.00 0 0 0 0 100
0 31 0.00 0 0.00 0.00 0 0.00 0 0 0 0 100
--
kiyohara
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Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 1.6ZH (MAGICIAN) #0: Fri Feb 13 02:40:04 JST 2004
lance@highpriestess.fool:/usr/src/sys/arch/cobalt/compile/MAGICIAN
256 MB memory, 247 MB freemainbus0 (root)
com0 at mainbus0 addr 0x1c800000 level 3: st16650a, working fifo
com0: console
cpu0 at mainbus0: QED RM5200 CPU (0x28a0) Rev. 10.0 with built-in FPU Rev. 10.0
cpu0: 32KB/32B 2-way set-associative L1 Instruction cache, 48 TLB entries
cpu0: 32KB/32B 2-way set-associative write-back L1 Data cache
panel0 at mainbus0 addr 0x1f000000
gt0 at mainbus0 addr 0x14000000
pci0 at gt0
pci0: i/o space, memory space enabled, rd/line, wr/inv ok
pchb0 at pci0 dev 0 function 0: Galileo GT-64111 System Controller, rev 1
tlp0 at pci0 dev 7 function 0: DECchip 21143 Ethernet, pass 4.1
tlp0: interrupting at level 1
tlp0: Ethernet address 00:10:e0:00:5b:b3
lxtphy0 at tlp0 phy 1: LXT970 10/100 media interface, rev. 3
lxtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
pcib0 at pci0 dev 9 function 0
pcib0: VIA Technologies VT82C586 (Apollo VP) PCI-ISA Bridge, rev 39
viaide0 at pci0 dev 9 function 1
viaide0: VIA Technologies VT82C586 (Apollo VP) ATA33 controller
viaide0: bus-master DMA support present
viaide0: primary channel configured to compatibility mode
viaide0: primary channel interrupting at irq 14
atabus0 at viaide0 channel 0
viaide0: secondary channel configured to compatibility mode
viaide0: secondary channel interrupting at irq 15
atabus1 at viaide0 channel 1
uhci0 at pci0 dev 9 function 2: VIA Technologies VT83C572 USB Controller (rev. 0x02)
uhci0: can't map i/o space
uhci1 at pci0 dev 10 function 0: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci1: interrupting at irq 9
usb0 at uhci1: USB revision 1.0
uhub0 at usb0
uhub0: VIA Technologies UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub0: 2 ports with 2 removable, self powered
uhci2 at pci0 dev 10 function 1: VIA Technologies VT83C572 USB Controller (rev. 0x61)
uhci2: interrupting at irq 0
usb1 at uhci2: USB revision 1.0
uhub1 at usb1
uhub1: VIA Technologies UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub1: 2 ports with 2 removable, self powered
VIA Technologies VT8237 EHCI USB Controller (USB serial bus, interface 0x20, revision 0x62) at pci0 dev 10 function 2 not configured
fwohci0 at pci0 dev 10 function 3: VIA Technologies VT3606 OHCI IEEE 1394 Controller (rev. 0x46)
fwohci0: interrupting at irq 0
fwohci0: OHCI 1.0, 00:40:26:01:08:08:19:30, 400Mb/s, 2048 max_rec, 8 ir_ctx, 8 it_ctx
tlp1 at pci0 dev 12 function 0: DECchip 21143 Ethernet, pass 4.1
tlp1: interrupting at level 2
tlp1: Ethernet address 00:10:e0:00:55:b6
lxtphy1 at tlp1 phy 1: LXT970 10/100 media interface, rev. 3
lxtphy1: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
IPsec: Initialized Security Association Processing.
fw0 at fwohci0: 00:40:26:01:08:08:19:30:0a:02:ff:ff:f0:01:00:00
uplcom0 at uhub1 port 1
uplcom0: vendor 0x067b product 0x2303, rev 1.10/2.00, addr 2
ucom0 at uplcom0
uftdi0 at uhub0 port 2
uftdi0: FTDI USB HS SERIAL CONVERTER, rev 1.10/2.00, addr 2
ucom1 at uftdi0 portno 1: portno 1
wd0 at atabus0 drive 0: <QUANTUM FIREBALL CR4.3A>
wd0: drive supports 16-sector PIO transfers, LBA addressing
wd0: 4110 MB, 14848 cyl, 9 head, 63 sec, 512 bytes/sect x 8418816 sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 4 (Ultra/66)
wd0(viaide0:0:0): using PIO mode 4, Ultra-DMA mode 2 (Ultra/33) (using DMA data transfers)
boot device: wd0
root on wd0a dumps on wd0b
root file system type: ffs
... snip ...
magician# fwnode0 at fwohci0 Node 1: UID 00:00:00:00:00:00:00:00
fwnode1 at fwohci0 Node 1: UID 00:d0:4b:01:00:01:01:48
fwnode0 detached
fwnode1: Link Speed: 100Mb/s, max_rec: 64 bytes
sbpscsi0 at fwnode1
scsibus0 at sbpscsi0: 1 target, 1 lun per target
sd0 at scsibus0 target 0 lun 0: <IC35L040, AVER07-0, ER4O> simplified direct fixed
sd0: 39266 MB, 39266 cyl, 64 head, 32 sec, 512 bytes/sect x 80418240 sectors
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Content-Disposition: inline; filename="cobalt_multifuncpci2.diff"
Index: arch/cobalt/dev/gt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/dev/gt.c,v
retrieving revision 1.9
diff -c -r1.9 gt.c
*** arch/cobalt/dev/gt.c 2003/07/15 01:29:23 1.9
--- arch/cobalt/dev/gt.c 2004/02/11 14:00:22
***************
*** 42,54 ****
--- 42,61 ----
#include <sys/syslog.h>
#include <sys/types.h>
#include <sys/device.h>
+ #include <sys/extent.h>
+ #include <sys/malloc.h>
#include <machine/intr.h>
#include <machine/bus.h>
#include <dev/pci/pcivar.h>
+ #include "opt_pci.h"
#include "pci.h"
+ #ifdef PCI_NETBSD_CONFIGURE
+ #include <dev/pci/pciconf.h>
+ #endif
+
struct gt_softc {
struct device sc_dev;
};
***************
*** 76,81 ****
--- 83,91 ----
void *aux;
{
struct pcibus_attach_args pba;
+ #ifdef PCI_NETBSD_CONFIGURE
+ struct extent *ioext, *memext;
+ #endif
printf("\n");
***************
*** 84,89 ****
--- 94,110 ----
(*((volatile u_int32_t *)0xb4000c00) & ~0x6) | 0x2;
#if NPCI > 0
+ #ifdef PCI_NETBSD_CONFIGURE
+ ioext = extent_create(
+ "pciio", 0x10100000, 0x11ffffff, M_DEVBUF, NULL, 0, EX_NOWAIT);
+ memext = extent_create(
+ "pcimem", 0x12000000, 0x13ffffff, M_DEVBUF, NULL, 0, EX_NOWAIT);
+ pci_configure_bus(0, ioext, memext, NULL, 0, 0);
+ /*
+ pc->memext = memext;
+ pc->ioext = ioext;
+ */
+ #endif
pba.pba_busname = "pci";
pba.pba_dmat = &pci_bus_dma_tag;
pba.pba_dmat64 = NULL;
Index: arch/cobalt/include/pci_machdep.h
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/include/pci_machdep.h,v
retrieving revision 1.5
diff -c -r1.5 pci_machdep.h
*** arch/cobalt/include/pci_machdep.h 2002/05/15 19:23:53 1.5
--- arch/cobalt/include/pci_machdep.h 2004/02/11 14:00:22
***************
*** 34,39 ****
--- 34,40 ----
* Machine-specific definitions for PCI autoconfiguration.
*/
#define __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
+ #define __HAVE_PCI_CONF_HOOK
/*
* Forward declarations.
***************
*** 72,77 ****
--- 73,80 ----
void *pci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
int, int (*)(void *), void *);
void pci_intr_disestablish(pci_chipset_tag_t, void *);
+ void pci_conf_interrupt(void *, int, int, int, int, int *);
+ int pci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t);
#define pci_enumerate_bus(sc, m, p) \
pci_enumerate_bus_generic((sc), (m), (p))
Index: arch/cobalt/pci/pci_machdep.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/pci/pci_machdep.c,v
retrieving revision 1.15
diff -c -r1.15 pci_machdep.c
*** arch/cobalt/pci/pci_machdep.c 2003/09/12 17:55:52 1.15
--- arch/cobalt/pci/pci_machdep.c 2004/02/11 14:00:22
***************
*** 34,39 ****
--- 34,40 ----
#include <sys/systm.h>
#include <sys/errno.h>
#include <sys/device.h>
+ #include <sys/extent.h>
#define _COBALT_BUS_DMA_PRIVATE
#include <machine/bus.h>
***************
*** 42,47 ****
--- 43,49 ----
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcidevs.h>
+ #include <dev/pci/pciconf.h>
/*
* PCI doesn't have any special needs; just use
***************
*** 223,226 ****
--- 225,251 ----
/* Try both, only the valid one will disestablish. */
cpu_intr_disestablish(cookie);
icu_intr_disestablish(cookie);
+ }
+
+ void
+ pci_conf_interrupt(pc, bus, dev, pin, swiz, iline)
+ pci_chipset_tag_t pc;
+ int bus, dev, pin, swiz, *iline;
+ {
+ /* not yet... */
+ }
+
+ int
+ pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
+ {
+ if ((PCI_VENDOR(id) == PCI_VENDOR_GALILEO &&
+ PCI_PRODUCT(id) == PCI_PRODUCT_GALILEO_GT64011)) {
+ /* Don't configure the bridge and PCI probe. */
+ return 0;
+ }
+ /* Don't configure device 9 */
+ if (dev == 9) return 0;
+
+ return PCI_CONF_ALL & ~(PCI_CONF_MAP_ROM |
+ PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE);
}
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Index: dev/pci/pciconf.c
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pciconf.c,v
retrieving revision 1.22
diff -c -r1.22 pciconf.c
*** dev/pci/pciconf.c 2003/12/02 16:31:06 1.22
--- dev/pci/pciconf.c 2004/02/11 14:01:53
***************
*** 1002,1008 ****
class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG);
misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG);
cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
! cmd |= PCI_COMMAND_SERR_ENABLE | PCI_COMMAND_PARITY_ENABLE;
if (pb->fast_b2b)
cmd |= PCI_COMMAND_BACKTOBACK_ENABLE;
if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
--- 1002,1011 ----
class = pci_conf_read(pd->pc, pd->tag, PCI_CLASS_REG);
misc = pci_conf_read(pd->pc, pd->tag, PCI_BHLC_REG);
cmd = pci_conf_read(pd->pc, pd->tag, PCI_COMMAND_STATUS_REG);
! if (pd->enable & PCI_CONF_ENABLE_PARITY)
! cmd |= PCI_COMMAND_PARITY_ENABLE;
! if (pd->enable & PCI_CONF_ENABLE_SERR)
! cmd |= PCI_COMMAND_SERR_ENABLE ;
if (pb->fast_b2b)
cmd |= PCI_COMMAND_BACKTOBACK_ENABLE;
if (PCI_CLASS(class) != PCI_CLASS_BRIDGE ||
Index: dev/pci/pciconf.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pciconf.h,v
retrieving revision 1.7
diff -c -r1.7 pciconf.h
*** dev/pci/pciconf.h 2002/09/28 10:31:02 1.7
--- dev/pci/pciconf.h 2004/02/11 14:01:53
***************
*** 55,59 ****
#define PCI_CONF_ENABLE_IO 0x08
#define PCI_CONF_ENABLE_MEM 0x10
#define PCI_CONF_ENABLE_BM 0x20
! #define PCI_CONF_ALL 0x3f
--- 55,61 ----
#define PCI_CONF_ENABLE_IO 0x08
#define PCI_CONF_ENABLE_MEM 0x10
#define PCI_CONF_ENABLE_BM 0x20
+ #define PCI_CONF_ENABLE_PARITY 0x40
+ #define PCI_CONF_ENABLE_SERR 0x80
! #define PCI_CONF_ALL 0xff
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