In article <20031123232019.GD274@merlin.camelot.net>
cdi@mawhrin.net wrote:

>  I'll definitely take a look at what sgimips does, thanks.

Maybe it's also worth to try pci_configure_bus(9) like bebox or prep etc.

> > Maybe it's worth to add some fixup code into gt.c:gt_attach().
> > (siop on my RaQ2 also requires fixup mem address space.)
> 
>  Tried that, with no visible effect. I must say I am no MIPS/kernel expert,
> and might well done a bogus fix, so just for the record I am attaching what I
> have tried. It's quick-and-dirty, but I think it mimics what Linux does.

options PCI_CONFIG_DUMP shows which values are set for
all PCI devices, so you can see if fixup is needed or not.
I'm using the following patch to fixup siop mem space.
It seems even Linux doesn't support memory space access of
any PCI devices because a comment in pci.c says "Fixup base
addresses, we only support I/O at the moment."
---
Izumi Tsutsui
tsutsui@ceres.dti.ne.jp


Index: dev/gt.c
===================================================================
RCS file: /cvsroot/src/sys/arch/cobalt/dev/gt.c,v
retrieving revision 1.9
diff -u -r1.9 gt.c
--- dev/gt.c	15 Jul 2003 01:29:23 -0000	1.9
+++ dev/gt.c	24 Nov 2003 01:01:18 -0000
@@ -47,6 +47,7 @@
 #include <machine/bus.h>
 
 #include <dev/pci/pcivar.h>
+#include <dev/pci/pcireg.h>
 #include "pci.h"
 
 struct gt_softc {
@@ -76,12 +77,20 @@
 	void *aux;
 {
 	struct pcibus_attach_args pba;
+	pcitag_t tag;
+	pcireg_t csr;
 
 	printf("\n");
 
 	/* XXX */
 	*((volatile u_int32_t *)0xb4000c00) =
 		(*((volatile u_int32_t *)0xb4000c00) & ~0x6) | 0x2;
+
+	/* fixup siop */
+	tag = pci_make_tag(NULL, 0, 8, 0);
+	csr = pci_conf_read(NULL, tag, 0x14);
+	csr |= 0x00100000;
+	pci_conf_write(NULL, tag, 0x14, csr);
 
 #if NPCI > 0
 	pba.pba_busname = "pci";