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On Mon, Nov 24, 2003 at 02:20:57AM +0900, Izumi Tsutsui wrote:
> According to arch/mips/cobalt/pci.c in linux-2.0.34C53_SK,
> some cobalt models require several pci fixup code (like sgimips does)
> including interrupt lines.

 I'll definitely take a look at what sgimips does, thanks.

 FWIW, I am using the followign Linux patch as a reference (don't remember
where I found it any longer):

 ftp://ftp.netbsd.org/pub/NetBSD/misc/cdi/Cobalt-2.4.0.patch.txt

> Maybe it's worth to add some fixup code into gt.c:gt_attach().
> (siop on my RaQ2 also requires fixup mem address space.)

 Tried that, with no visible effect. I must say I am no MIPS/kernel expert,
and might well done a bogus fix, so just for the record I am attaching what I
have tried. It's quick-and-dirty, but I think it mimics what Linux does.

Thanks for your help!

SY,
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diff -u -r src/sys/arch/cobalt/cobalt/machdep.c lcdcons/arch/cobalt/cobalt/machdep.c
--- src/sys/arch/cobalt/cobalt/machdep.c	Mon Jan 14 00:02:33 2002
+++ lcdcons/arch/cobalt/cobalt/machdep.c	Sun Nov  9 20:42:03 2003
@@ -527,6 +527,15 @@
 		netintr();
 	}
 
+#define	STATUSF_IP3	(1   << 11)
+	if (ipending & STATUSF_IP3) {
+		extern int	(* tlp_intr_fptr)(void *);
+		extern void	*tlp_intr_arg;
+
+/*		printf("cpu_intr: 0x%x - 0x%x\n", cause, ipending);*/
+		tlp_intr_fptr(tlp_intr_arg);
+	}
+
 	/* 'softclock' interrupt */
 	if (ipending & MIPS_SOFT_INT_MASK_0) {
 		clearsoftclock();
diff -u -r src/sys/arch/cobalt/dev/gt.c lcdcons/arch/cobalt/dev/gt.c
--- src/sys/arch/cobalt/dev/gt.c	Thu May 16 03:01:35 2002
+++ lcdcons/arch/cobalt/dev/gt.c	Wed Oct 22 21:47:18 2003
@@ -67,6 +67,8 @@
 	return 1;
 }
 
+void kcomprint(const char *s);
+
 static void
 gt_attach(parent, self, aux)
 	struct device *parent;
@@ -90,6 +92,27 @@
 	pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
 		PCI_FLAGS_MRL_OKAY | /*PCI_FLAGS_MRM_OKAY|*/ PCI_FLAGS_MWI_OKAY;
 	config_found(self, &pba, gt_print);
+
+	{
+		pcireg_t galileo_id;
+
+		printf("\n\n=================================\n");
+		printf("Get Galileo id\n");
+		galileo_id = pci_conf_read(pba.pba_pc, 0x0, PCI_CLASS_REG);
+		galileo_id &= PCI_CLASS_MASK;
+		printf("Galileo id is: %u\n", galileo_id);
+		if (galileo_id == 0x10) {
+			/* New Galileo, assumes PCI stop line to VIA is connected. */
+			*((volatile u_int32_t *)0xb4000c04) = 0x00004020;
+		} else if (galileo_id == 0x1 || galileo_id == 0x2) {
+			unsigned int timeo;
+			/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
+			timeo = *((volatile u_int32_t *)0xb4000c04);
+			/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
+			*((volatile u_int32_t *)0xb4000c04) = 0x0000ffff;
+		}
+		printf("=================================\n\n");
+	}
 #endif
 	return;
 }
diff -u -r src/sys/arch/cobalt/pci/pci_machdep.c lcdcons/arch/cobalt/pci/pci_machdep.c
--- src/sys/arch/cobalt/pci/pci_machdep.c	Mon Jan 14 00:02:35 2002
+++ lcdcons/arch/cobalt/pci/pci_machdep.c	Sun Nov  9 20:36:17 2003
@@ -41,6 +41,8 @@
 #include <dev/pci/pcireg.h>
 #include <dev/pci/pcidevs.h>
 
+#define __UTILIZE_IRQ_13	1
+
 /*
  * PCI doesn't have any special needs; just use
  * the generic versions of these functions.
@@ -104,6 +106,8 @@
 #define PCI_CFG_ADDR	((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x14000cf8))
 #define PCI_CFG_DATA	((volatile u_int32_t *)MIPS_PHYS_TO_KSEG1(0x14000cfc))
 
+void kcomprint(const char *);
+
 pcireg_t
 pci_conf_read(pc, tag, reg)
 	pci_chipset_tag_t pc;
@@ -118,13 +122,17 @@
 	/*
 	 * 2700 hardware wedges on accesses to device 6.
 	 */
-	if (bus == 0 && dev == 6)
+	if (bus == 0 && dev == 6) {
+		kcomprint("bus == 0, dev == 6");
 		return 0;
+	}
 	/*
 	 * 2800 hardware wedges on accesses to device 31.
 	 */
-	if (bus == 0 && dev == 31)
+	if (bus == 0 && dev == 31) {
+		kcomprint("bus == 0, dev == 31");
 		return 0;
+	}
 
 	*PCI_CFG_ADDR = 0x80000000 | tag | reg;
 	data = *PCI_CFG_DATA;
@@ -165,9 +173,14 @@
 	 * directly to the CPU.
 	 */
 
-	if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A)
+	if (bus == 0 && dev == 7 && pin == PCI_INTERRUPT_PIN_A) {
+#ifndef __UTILIZE_IRQ_13
 		*ihp = 16 + 1;
-	else if (bus == 0 && dev == 12 && pin == PCI_INTERRUPT_PIN_A)
+#else
+		*ihp = 13;
+		pci_conf_write(pc, intrtag, PCI_INTERRUPT_REG, 13);
+#endif
+	} else if (bus == 0 && dev == 12 && pin == PCI_INTERRUPT_PIN_A)
 		*ihp = 16 + 2;
 	else
 		*ihp = line;
@@ -200,6 +213,9 @@
 	return NULL;
 }
 
+int	(* tlp_intr_fptr)(void *);
+void	*tlp_intr_arg;
+
 void *
 pci_intr_establish(pc, ih, level, func, arg)
 	pci_chipset_tag_t pc;
@@ -207,6 +223,21 @@
 	int level, (*func)(void *);
 	void *arg;
 {
+#ifdef __UTILIZE_IRQ_13
+	if (ih == 13) {
+		void *cookie;
+		printf("Establishing Tulip interrupt.\n");
+		cookie = icu_intr_establish(13, IST_EDGE, IPL_BIO, func, arg);
+
+		tlp_intr_fptr = func;
+		tlp_intr_arg  = arg;
+
+		if (cookie == NULL)
+			return (NULL);
+		printf("my_tlp0: interrupting at irq %d\n", ih);
+		return (cookie);
+	} else
+#endif
 	if (ih >= 16)
 		return cpu_intr_establish(ih - 16, level, func, arg);
 	else

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