David Brownlee wrote:

> On Wed, 12 Jun 2002, Jason R Thorpe wrote:
>
> > On Wed, Jun 12, 2002 at 10:15:50AM +0100, David Brownlee wrote:
> >  >    Presumably the kernel can determine at runtime whether the
> >  >    current CPU supports the atomic TAS instructions?
> >
> > Beyond taking an illegal insn trap, no.  Or having a table of models that
> > don't support it (no mips1 supports it, almost all mips3, mips32, mips64,
> > etc. CPUs support it, except for a few).

Somewhat annoyingly, all(?) the HPC MIPS based machines use CPUs that don't
support LL/SC either.

> > We need to solve this problem for the new pthread library, too.  I think
> > the solution there was to use restartable sequences on CPUs which don't
> > have the LL/SC insns.  (Though, the solution has not yet been implemented.)
> 
> 	Is there any sense in having libc atomic TAS functions which can
> 	be implemented using the lowest common denominator on each arch,
> 	and then overridden with the ld.so.conf sysctl check where
> 	appropriate, or is that too much overhead?

From memory, the restartable sequences paper actually mentioned that
they were faster in the general case for CPUs that supported a LL/SC
style TAS too.  I can't remember the SMP implications though...

Simon.
--
Simon Burge                            <simonb@wasabisystems.com>
NetBSD Support and Service:         http://www.wasabisystems.com/