On Wed, Jun 12, 2002 at 10:15:50AM +0100, David Brownlee wrote:

 > 	Presumably the kernel can determine at runtime whether the
 > 	current CPU supports the atomic TAS instructions?

Beyond taking an illegal insn trap, no.  Or having a table of models that
don't support it (no mips1 supports it, almost all mips3, mips32, mips64,
etc. CPUs support it, except for a few).

 > 	If it exported this information via a machdep sysctl then we could
 > 	have 'MIPS1' and 'LL/SC' versions of the operations in separate
 > 	libraries and then select between them in ld.so.conf (similar to
 > 	i386 with libm387.so.0).

We need to solve this problem for the new pthread library, too.  I think
the solution there was to use restartable sequences on CPUs which don't
have the LL/SC insns.  (Though, the solution has not yet been implemented.)

-- 
        -- Jason R. Thorpe <thorpej@wasabisystems.com>
	...at USENIX...