Hi,

now I have some new informations about the TC1006 graficcard:

There is a TCL 34075 (Texas) RAMDAC on the card.
I found some informations about these chip in "ramdac.txt" from the
vgadoc4b.zip archive.

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TI TLC34075, ATI68875 True color DACs
This DAC has an 8bit VGA port and a 32bit pixelport (P). The 32bit pixelport
P can be multiplexed for greater bandwidth. 6 or 8 bit DACs can be controlled
via the 8/6 pin (low=6bit, high=8bit).

REG08 (R/W):  General Control Register
bit    0  If set HSYNCOUT is active high, active low if clear
       1  If set VSYNCOUT is active high, active low if clear
       2  Enables split shift register transfer (VRAM) if set
       3  Enables special nibble mode if set
       4  Pedestal Enable Control. Set for a 7.5 IRE pedestal, clear for a 0
          IRE pedestal
       5  Sync Enable Control. If set enables sync on green.
       7  MUXOUT. If set the MUXOUT output pin is high, low if clear
Note: bits 2 and 3 can not both be set.

REG09 (R/W):  Input Clock Selection Register
bit  0-3  Selects the clock source (DOTCLK):
            0: CLK0, 1: CLK1, 2: CLK2, 3: CLK3 (TTL), 4: /CLK3 (TTL)
            8: CLK3 and /CLK3 are selected as an ECL clock source

REG0A (R/W):  Output Clock Selection Register
bit  0-2  Selects SCLK from DOTCLK.
            0: SCLK=DOTCLK, 1: SCLK=DOTCLK/2, 2: SCLK=DOTCLK/4
            3: SCLK=DOTCLK/8, 4: SCLK=DOTCLK/16, 5: SCLK=DOTCLK/32
            6,7: SCLK held at logic low
     3-5  Selects VCLK from DOTCLK.
            0: VCLK=DOTCLK, 1: VCLK=DOTCLK/2, 2: VCLK=DOTCLK/4
            3: VCLK=DOTCLK/8, 4: VCLK=DOTCLK/16, 5: VCLK=DOTCLK/32
            6,7: VCLK held at logic high

REG0B (R/W):  MUX Control Register
bit  0-5  Selects bits/pixel, pixel port and multiplexing:
            0Dh  24bpp from P. Red=P8-15, Green=P16-23, Blue=P24-31
            10h  1bpp. 4 pixels/DOTCLK from P0-3
            11h  1bpp. 8 pixels/DOTCLK from P0-7
            12h  1bpp. 16 pixels/DOTCLK from P0-15
            13h  1bpp. 32 pixels/DOTCLK from P0-31
            14h  2bpp. 2 pixels/DOTCLK from P0-3
            15h  2bpp. 4 pixels/DOTCLK from P0-7
            16h  2bpp. 8 pixels/DOTCLK from P0-15
            17h  2bpp. 16 pixels/DOTCLK from P0-31
            18h  4bpp. 1 pixel/DOTCLK from P0-3
            19h  4bpp. 2 pixels/DOTCLK from P0-7
            1Ah  4bpp. 4 pixels/DOTCLK from P0-15
            1Bh  4bpp. 8 pixels/DOTCLK from P0-31
            1Ch  8bpp. 1 pixels/DOTCLK from P0-7
            1Dh  8bpp. 2 pixels/DOTCLK from P0-15
            1Eh  8bpp. 4 pixels/DOTCLK from P0-31
            1Fh  4bpp. 4 pixels/DOTCLK from P0-31   (Special Nibble mode)
                 If the NFLAG input is low the 4 pixels are from P0-3, P8-11,
                 P16-19, P24-27 if high from P4-7, P12-15, P20-23, P28-31
            2Dh  8bpp from VGA port

REG0C (R/W):  Palette Page Register
bit  0-7  For 1,2 and 4 bits/pixel modes the upper bits of this register are
          used to select 1 of 128, 64 and 16 pages respectively in the
          palette RAM. The pixel data selects the entry within the page.

REG0E (R/W):  Test Register
bit  0-2  (W) Test mode. Selects the current test mode. Reading this register
              will step to the next test (see Next below).
              Val:  Next:    Description:
               0      1      Read Color Palette Red value
               1      2      Read Color Palette Green value
               2      0      Read Color Palette Blue value
               3      0      Read Identification code.
                             Returns 75h for 34075
               4      5      Read Ones Accumulation Red value
               5      6      Read Ones Accumulation Green value
               6      4      Read Ones Accumulation Blue value
               7      7      Analog Test. Result specified below.
       3  (R) Analog Test result. Set if the voltage selected by bit 6 (Green)
               or bit 7 (Red) is larger than the one selected by bit 4 (145mV
               reference) or bit 5 (Blue), clear if not.
       4  Select 145mV reference if set. Only applies to Analog test (bit 0-2
           = 7)
       5  Select Blue DAC if set. Only applies to Analog test (bit 0-2 = 7)
       6  Select Green DAC if set. Only applies to Analog test (bit 0-2 = 7)
       7  Select Red DAC if set. Only applies to Analog test (bit 0-2 = 7)

REG0F (W):  Reset State
Note: Writing to this register will cause a hardware reset of the DAC.
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Now I want to find out where exact the registers are. The range is between
FEFF.0000 to FEFF.FFFF (64K).


Greetings, Holger