> > The ARM ARM defines two (plus a deprecated third) abort models --
> > 
> > Base restored: The base register is always the value before the 
> > instruction started execution.
> 
> No such luck :-(

Pity :-(

> 
> > Base updated: The base register is always the value after an
> > post-addressing side-effect has been applied
> 
> This is the one, I hope :-)

Yep, that's my understanding from the 7TDMI data sheet too.  Oh well, time 
someone put in code to (at least) detect the presence of an abort in Thumb 
mode and segfault the program (at present who knows what will happen).

> 
> > Early abort (deprecated): LDC, LDM, STC & STM instructions have 
> > post-addressing side-effects applied, other instructions do not.
> 
> I hope not. The 7tdmi docs don't say anything about fixing up stc
> insns.

Hm, although its possible to put a co-processor which uses ldc/stc on the 
7tdmi, I doubt that the Psion chips have one.  Not that it matters in this 
case, since this abort model doesn't exist on the 7TDMI!

> 
> > Some documents refer to late-abort: this is identical to Base
> > Updated.
> 
> Unfortunately I couldn't find any handy keywords anywhere to describe
> the 7tdmi model (probably not looking in the right place).

It doesn't say, but from what it does say it's clearly base-updated (aka 
late aborts).

> Thank you for the explanations! 

No problem.

R.