Richard Earnshaw <rearnsha@arm.com> writes:

> > Ben Harris <bjh21@netbsd.org> writes:
> > 
> > [...]
> > 
> > > > It doesn't give me a handy keyword. For data abt, ldr and str can
> > > > apparently write back modified base registers, and ldm and stm insns
> > > > can abort sort of halfway through. I guess this is the ARM6 early abt
> > > > model?
> > > 
> > > Writing back modified base registers for LDR and STR is the "Base
> > > Updated Abort Model", ie late aborts. 
> > 
> > So I want the arm7 fixups like I originally tried?
> 
> Just to clarify.
> 
> The ARM ARM defines two (plus a deprecated third) abort models --
> 
> Base restored: The base register is always the value before the 
> instruction started execution.

No such luck :-(

> Base updated: The base register is always the value after an
> post-addressing side-effect has been applied

This is the one, I hope :-)

> Early abort (deprecated): LDC, LDM, STC & STM instructions have 
> post-addressing side-effects applied, other instructions do not.

I hope not. The 7tdmi docs don't say anything about fixing up stc
insns.

> Some documents refer to late-abort: this is identical to Base
> Updated.

Unfortunately I couldn't find any handy keywords anywhere to describe
the 7tdmi model (probably not looking in the right place).

> In all cases, if a load multiple updates the base-register with a
> value from memory and then aborts on a later word the base register
> is restored to its original value.

> If you have the choice, use the Base Restored model since it saves
> the need to disassemble the instruction and potentially undo
> side-effects -- an issue that becomes particularly tedious if you
> also have to handle Thumb code.

Good point. I don't think the current data abt fix ups handle
Thumb. Something to do on a rainy day perhaps.

Thank you for the explanations! 

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