Subject: The first Netwinder dmesg!
To: None <port-arm32@netbsd.org>
From: Matt Thomas <matt@3am-software.com>
List: port-arm32
Date: 04/19/2001 20:21:23
Note that the Netwinder BIOS doesn't actually initialize everything.
Which is why the tlp & ne failed to init. Why did this boot? What
did I change? I cheated! I start physical_freespace at 2MB and
map the using two PD Section Descriptors. I eventually fix that but
for now I can see ...
NetBSD/netwinder booting ...
initarm: Configuring system ...
physmemory: 16384 pages at 0x00000000 -> 0x03ffffff
Allocating page tables
freestart = 0x200000, free_pages = 15872 (0x3e00)
IRQ stack: p0x00220000 v0xf0220000
ABT stack: p0x00221000 v0xf0221000
UND stack: p0x00222000 v0xf0222000
SVC stack: p0x00223000 v0xf0223000
Creating L1 page table at 0x200000
Mapping kernel
Constructing L2 page tables
map_chunk: pa=220000 va=f0220000 sz=1000 rem=1000 acc=1 flg=c
map_chunk: P
map_chunk: pa=221000 va=f0221000 sz=1000 rem=1000 acc=1 flg=c
map_chunk: P
map_chunk: pa=222000 va=f0222000 sz=1000 rem=1000 acc=1 flg=c
map_chunk: P
map_chunk: pa=223000 va=f0223000 sz=2000 rem=2000 acc=1 flg=c
map_chunk: PP
map_chunk: pa=200000 va=f0200000 sz=4000 rem=4000 acc=1 flg=0
map_chunk: PPPP
42000000 -> 420fffff @ fd000000
50000000 -> 500fffff @ fd100000
7c000000 -> 7c0fffff @ fd200000
79000000 -> 790fffff @ fd300000
7a000000 -> 7affffff @ fe000000
7b000000 -> 7bffffff @ ff000000
80000000 -> 800fffff @ fd400000
freestart = 0x226000, free_pages = 15834 (0x3dda)
switching to new L1 page table @0x200000...done!
bootstrap done.
init subsystems: stacks vectors undefined pmap irq done.
ddb: Copyright (c) 1996, 1997, 1998, 1999, 2000, 2001
The NetBSD Foundation, Inc. All rights reserved.
Copyright (c) 1982, 1986, 1989, 1991, 1993
The Regents of the University of California. All rights reserved.
NetBSD 1.5U (GENERIC) #38: Thu Apr 19 23:38:39 UTC 2001
matt@tiger.local:/other/netwinder/kobj/GENERIC
total memory = 65536 KB
avail memory = 57332 KB
using 614 buffers containing 3376 KB of memory
mainbus0 (root)
cpu0 at mainbus0: SA-110 rev 4 (SA-1 core) DC enabled IC enabled WB enabled
EABT
footbridge0 at mainbus0: DC21285 rev 3
pci0 at footbridge0 bus 0
pci0: i/o space, memory space enabled
Integraphics Systems product 0x2010 (VGA display, revision 0x01) at pci0
dev 8 function 0: PCI configuration registers:
Common header:
0x00: 0x201010ea 0x02000002 0x03000001 0x00000000
Vendor Name: Integraphics Systems (0x10ea)
Device ID: 0x2010
Command register: 0x0002
I/O space accesses: off
Memory space accesses: on
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Status register: 0x0200
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: display (0x03)
Subclass Name: VGA (0x00)
Interface: 0x00
Revision ID: 0x01
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x08000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x02020202
0x30: 0xffff0000 0x00000000 0x00000000 0x000001ff
Base address register at 0x10
type: 32-bit nonprefetchable memory
base: 0x08000000, size: 0x01000000
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0202
Subsystem ID: 0x0202
Expansion ROM Base Address: 0xffff0000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x01 (pin A)
Interrupt line: 0xff
Device-dependent header:
0x40: 0x00000000 0x00000000 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Integraphics Systems product 0x2010 (VGA display, revision 0x01) at pci0
dev 8 function 0 (tag 0x4000, intrtag 0x4000, intrswiz 0, intrpin 0x1, i/o
off, mem on, no quirks) not configured
tlp0 at pci0 dev 9 function 0: PCI configuration registers:
Common header:
0x00: 0x00191011 0x02800000 0x02000041 0x00002020
Vendor Name: Digital Equipment (0x1011)
Device Name: DECchip 21142/21143 10/100 Ethernet (0x0019)
Command register: 0x0000
I/O space accesses: off
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Status register: 0x0280
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: network (0x02)
Subclass Name: ethernet (0x00)
Interface: 0x00
Revision ID: 0x41
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x20
Cache Line Size: 0x20
Type 0 ("normal" device) header:
0x10: 0xddfbfc01 0x20000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x5554574e
0x30: 0xbffc0000 0x00000000 0x00000000 0x28140109
Base address register at 0x10
type: 32-bit i/o
base: 0xddfbfc00, size: 0x00000080
Base address register at 0x14
type: 32-bit nonprefetchable memory
base: 0x20000000, size: 0x00000400
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x574e
Subsystem ID: 0x5554
Expansion ROM Base Address: 0xbffc0000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x28
Minimum Grant: 0x14
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x09
Device-dependent header:
0x40: 0x80000000 0x00000000 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Digital Equipment DECchip 21142/21143 10/100 Ethernet (ethernet network,
revision 0x41) at ? dev 9 function 0 (tag 0x4800, intrtag 0x4800, intrswiz
0, intrpin 0x1, i/o off, mem off, no quirks): DECchip 21143 Ethernet, pass 4.1
: unable to map device registers
Symphony Labs 83C553 PCI-ISA Bridge (ISA bridge, revision 0x10) at pci0 dev
11 function 0: PCI configuration registers:
Common header:
0x00: 0x056510ad 0x02000007 0x06010010 0x00800000
Vendor Name: Symphony Labs (0x10ad)
Device Name: 83C553 PCI-ISA Bridge (0x0565)
Command register: 0x0007
I/O space accesses: on
Memory space accesses: on
Bus mastering: on
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Status register: 0x0200
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: off
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: bridge (0x06)
Subclass Name: ISA (0x01)
Interface: 0x00
Revision ID: 0x10
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000000 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x00000000
Base address register at 0x10
not implemented(?)
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x00
Minimum Grant: 0x00
Interrupt pin: 0x00 (none)
Interrupt line: 0x00
Device-dependent header:
0x40: 0xef000420 0x00780000 0x00000001 0x00043300
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x800001e0 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x0a220000 0x00000101 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Symphony Labs 83C553 PCI-ISA Bridge (ISA bridge, revision 0x10) at pci0 dev
11 function 0 (tag 0x5800, intrtag 0x5800, intrswiz 0, intrpin 0, i/o on,
mem on, no quirks) not configured
Symphony Labs 82C105 (IDE mass storage, interface 0x8f, revision 0x05) at
pci0 dev 11 function 1: PCI configuration registers:
Common header:
0x00: 0x010510ad 0x02800001 0x01018f05 0x00802008
Vendor Name: Symphony Labs (0x10ad)
Device Name: 82C105 (0x0105)
Command register: 0x0001
I/O space accesses: on
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Status register: 0x0280
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: mass storage (0x01)
Subclass Name: IDE (0x01)
Interface: 0x8f
Revision ID: 0x05
BIST: 0x00
Header Type: 0x00+multifunction (0x80)
Latency Timer: 0x20
Cache Line Size: 0x08
Type 0 ("normal" device) header:
0x10: 0x000001f1 0x000003f5 0x00000171 0x00000375
0x20: 0x00000001 0x00000001 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x2802010e
Base address register at 0x10
type: 32-bit i/o
base: 0x000001f0, size: 0x00000008
Base address register at 0x14
type: 32-bit i/o
base: 0x000003f4, size: 0x00000004
Base address register at 0x18
type: 32-bit i/o
base: 0x00000170, size: 0x00000008
Base address register at 0x1c
type: 32-bit i/o
base: 0x00000374, size: 0x00000004
Base address register at 0x20
type: 32-bit i/o
base: 0x00000000, size: 0x00000010
Base address register at 0x24
type: 32-bit i/o
base: 0x00000000, size: 0x00000010
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x28
Minimum Grant: 0x02
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x0e
Device-dependent header:
0x40: 0x00ff0091 0x00000909 0x00000909 0x00000909
0x50: 0x00000909 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x000000ff
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Symphony Labs 82C105 (IDE mass storage, interface 0x8f, revision 0x05) at
pci0 dev 11 function 1 (tag 0x5900, intrtag 0x5900, intrswiz 0, intrpin
0x1, i/o on, mem off, no quirks) not configured
ne0 at pci0 dev 12 function 0: PCI configuration registers:
Common header:
0x00: 0x5a5a1050 0x02800001 0x02000000 0x00000000
Vendor Name: Winbond Electronics (0x1050)
Device Name: W89C940F Ethernet (0x5a5a)
Command register: 0x0001
I/O space accesses: on
Memory space accesses: off
Bus mastering: off
Special cycles: off
MWI transactions: off
Palette snooping: off
Parity error checking: off
Address/data stepping: off
System error (SERR): off
Fast back-to-back transactions: off
Status register: 0x0280
Capability List support: off
66 MHz capable: off
User Definable Features (UDF) support: off
Fast back-to-back capable: on
Data parity error detected: off
DEVSEL timing: medium (0x1)
Slave signaled Target Abort: off
Master received Target Abort: off
Master received Master Abort: off
Asserted System Error (SERR): off
Parity error detected: off
Class Name: network (0x02)
Subclass Name: ethernet (0x00)
Interface: 0x00
Revision ID: 0x00
BIST: 0x00
Header Type: 0x00 (0x00)
Latency Timer: 0x00
Cache Line Size: 0x00
Type 0 ("normal" device) header:
0x10: 0x00000301 0x00000000 0x00000000 0x00000000
0x20: 0x00000000 0x00000000 0x00000000 0x00000000
0x30: 0x00000000 0x00000000 0x00000000 0x08080100
Base address register at 0x10
type: 32-bit i/o
base: 0x00000300, size: 0x00000020
Base address register at 0x14
not implemented(?)
Base address register at 0x18
not implemented(?)
Base address register at 0x1c
not implemented(?)
Base address register at 0x20
not implemented(?)
Base address register at 0x24
not implemented(?)
Cardbus CIS Pointer: 0x00000000
Subsystem vendor ID: 0x0000
Subsystem ID: 0x0000
Expansion ROM Base Address: 0x00000000
Reserved @ 0x34: 0x00000000
Reserved @ 0x38: 0x00000000
Maximum Latency: 0x08
Minimum Grant: 0x08
Interrupt pin: 0x01 (pin A)
Interrupt line: 0x00
Device-dependent header:
0x40: 0x88888888 0x00000000 0x00000000 0x00000000
0x50: 0x00000000 0x00000000 0x00000000 0x00000000
0x60: 0x00000000 0x00000000 0x00000000 0x00000000
0x70: 0x00000000 0x00000000 0x00000000 0x00000000
0x80: 0x00000000 0x00000000 0x00000000 0x00000000
0x90: 0x00000000 0x00000000 0x00000000 0x00000000
0xa0: 0x00000000 0x00000000 0x00000000 0x00000000
0xb0: 0x00000000 0x00000000 0x00000000 0x00000000
0xc0: 0x00000000 0x00000000 0x00000000 0x00000000
0xd0: 0x00000000 0x00000000 0x00000000 0x00000000
0xe0: 0x00000000 0x00000000 0x00000000 0x00000000
0xf0: 0x00000000 0x00000000 0x00000000 0x00000000
Don't know how to pretty-print device-dependent header.
Winbond Electronics W89C940F Ethernet (ethernet network) at ? dev 12
function 0 (tag 0x6000, intrtag 0x6000, intrswiz 0, intrpin 0x1, i/o on,
mem off, no quirks): Winbond 89C940F Ethernet
ne0: Ethernet address 00:10:57:00:12:d0
pci_intr_map: no mapping for pin A
ne0: couldn't map interrupt
todclock0 at footbridge0
fcom at footbridge0 not configured
ipl_bio=00000000 ipl_net=00000000 ipl_tty=00000000 ipl_imp=00000000
ipl_audio=00000000 ipl_imp=00000000 ipl_high=00000000 ipl_serial=00000000
clock: hz=100 stathz = 0 profhz = 0
md0: allocated 0K (0 blocks)
boot device: <unknown>
root device:
--
Matt Thomas Internet: matt@3am-software.com
3am Software Foundry WWW URL: http://www.3am-software.com/bio/matt/
Cupertino, CA Disclaimer: I avow all knowledge of this message