> On Saturday 10 March 2001 10:18 am, Richard Earnshaw wrote:
> > > After some more tests, I'm more confused than before.
> > >
> > > Doing some thinking I suddenly vaguely remembered that the SA-110
> > > had a bug at some versions.
> > >
> > > As mine is second hand, I had a look on it and seems to be a revision
> > > 'S'.
> >
> > Rev S is OK.  It's what I've got.  It's rev K that has the problems.
> 
> So what was fixed in the rev T?  (hmm maybe we should stick this in the arm32 
> FAQ...)

I believe that fixes the LDMIB bug described in the Intel Specifiction 
Update (as they call them) [doc 278104-001]

Basically the conditions for the bug are:

LDMIB	Rn, {register list including Rn}
LDMIB causes data abort (for example by crossing a page boundary)
At least one register is successfully loaded before the abort occurs.

Under these circumstances the base register is incorrectly restored to 
base+4.  It is, in general, impossible to correctly unwind this fault, 
since you can't tell whether 0 or 1 registers were loaded before the abort 
occured.

Fortunately, gcc almost never generates LDMIB instructions.

R.