Thanks again for the info, I seems that the MMU is key to this, as Robert
Swindle also indicated in a follow-up. 

The IXP-1200 is not really a member of the XScale (faster StrongArms)
processor family. It is a network-processor, and is good for filtering at
network line speed. It is described at the developers section at
http://developer.intel.com/design/network/products/npfamily/ixp1200.htm, but
the memory maps for the device is found in the Programmers Reference Manual
(appendix C) which is on the developer CD.

Regards,
Kurt Alstrup

-----Original Message-----
From: Chris Gilbert [mailto:chris@buzzbee.freeserve.co.uk]
Sent: Friday, October 06, 2000 6:32 PM
To: Alstrup, Kurt; 'port-arm32@netbsd.org'
Subject: Re: Memory map guidelines


On Sat, 07 Oct 2000, Alstrup, Kurt wrote:
> Thanks for the info.
>
> The SA-1100 and IXP-1200 (the StrongArm core of the latter) both have the
> same MMU instructions as eg SA-110 has.
>
>  The problem is that the hardware I know (SA-110 + 21285 co-processor has
> it's RAM at address 0 and ROM somewhere else. This works only because the
> 21285 (aka footbridge) maps (they use the term alias in the specs) the ROM
> to address 0 in the time-window after reset and the first memory write.
> That window is enough to jump to the true ROM where the remainder of the
> bootstrap happens.
>
>  The IXP1200 does not (to my knowledge) perform that little trick, so my
> concern is if NetBSD has any dependencies/requirements regarding the
> physical
> location of ROM and RAM (e.g. must RAM be at address 0).

Hmmm, I'm sure that at some point we remap the kernel into the 0 page.  if 
you can do this with the MMU then you'd have rom at 0, this loads up the 
kernel into the ram, then calls the kernel (calling it's address would be 
like calling it's reset vector)  it could then map itself down into the 0 
page?

I don't know enough about the MMU to say if this is possible.

As for the IXP1200 surely the same trick could be done with hardware as with

the footbridge?  all it is is something that gets reset on the reset pin,
and 
then remaps on the first write pin high?

> I am tempted to put ROM at address 0 and RAM somewhere else. The reset
> vector would point at the ROM and the other vectors just re-direct to the
> bottom of the physical RAM. If this will work, then the next question is
> what configuration files need to be adjusted?

That would certainly sound possible.  Do you have a bootstrap rom already to

try these things out?  (I hate to say it but it might be a case of play with

some code and see if you can get it to do something?)

What is the IXP-1200 anyway?  is this part of intels new chip range base on 
the SA, I'm sure I saw an article on slashdot about a new chip range (called

Xscale?)
http://slashdot.org/articles/00/08/25/1155254.shtml

Chris