On Apr 7, Mike Pumford wrote
> I patched both the last working kernel I have (with v1.60) and the kernel 
> which fails to probe.
> 
> This is the standard RISCPC 1.4_ALPHA distribution kernel on ftp.netbsd.org 
> patched as described above.
> 
> The drive is the master on the primary device:
> 
> simide0 at podulebus0 [podule 1]:
> simide0:0: before reset, st0=0x50, st1=0x0
> simide0:0: wdcwait_reset() end, st0=0x50, st1=0x0
> simide0:0: after reset, ret_value=0x3
> simide0:0:0: after reset, sc=0x0 sn=0x27 cl=0x7a ch=0xc
> simide0:0:1: after reset, sc=0x0 sn=0x27 cl=0x7a ch=0xc
> simide0:0:1: not ready
> wdcattach: ch_drive_flags 0x4 0x0
> simide0:0: wdcwait_reset() end, st0=0x50, st1=0x0
> simide0:1: before reset, st0=0xff, st1=0xff

Well, i've at last found a bug: your drive should have been attached as
an ST506 :)

The problem here is that after the reset we read random values in the
registers instead of the required 'ata signature'.
Could you try to increase the delay() values ?
I saw this problem recently on a i386, the problem turned out to be
that on i386, delay(1) was equivalent to delay(0) (now fixed). I bumped
all delays to 10. Maybe it's not enouth for arm32 ?
Can you try to bump all delay(10) to delay(100) in sys/dev/ic/wdc.c ?
This should be safe, all delay(10) present here are not in an interrupt path
as far as I can tell ...

> 
> This is the last working kernel I built for myself again patched as described 
> above with the same hardware configuration.
> 
> simide0 at podulebus0 [ podule 1 ]:
> simide0:0: before reset, st0=0x50, st1=0x0
> simide0:0: after reset, ret_value=0x3
> simide0:0:0: after reset, sc=0x0 sn=0x1 cl=0x69 ch=0xd
> simide0:0:1: after reset, sc=0x0 sn=0x1 cl=0x69 ch=0xd
> simide0:0:1: not ready
> wdcattach: ch_drive_flags 0x1 0x0
> wd0 at simide0 channel 0 drive 0wdattach
> : <ST36451A>
> wd0: drive supports 16-sector pio transfers, lba addressing
> wd0: 6149MB, 13328 cyl, 15 head, 63 sec, 512 bytes/sect x 12594960 sectors
> wd0: atap_dmatiming_mimi=120, atap_dmatiming_recom=120
> wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 2
> simide0:1: before reset, st0=0xff, st1=0xff

Same problem here (random values in registers) but this code didn't rely on
ata signature.

--
Manuel Bouyer, LIP6, Universite Paris VI.           Manuel.Bouyer@lip6.fr
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