Just wondering if my idea can be applied to RiscBSD - I don't know about how 
the ARM FPE works, but this should considerably reduce the amount of time spent 
in the kernel by FP intensive apps.

For those who don't frequent c.s.a.programmer, my idea is essentially to 
have the handler for the FP instruction exception trap decode the arguments, 
put them in a table indexed by address then overwrite the FP instruction with a 
BL to some handler routine which would then pick the results from the table and 
emulate the instruction.  This should produce a considerable increase in speed 
and reduction of time spent in SVC mode.