On Oct 16,  8:52pm, Mark Smith wrote:
> Subject: Re: SA110 - Current status
> In message <9610151623.ZM7714@physig4.ph.kcl.ac.uk>
>           "Mark Brinicombe" <amb@physig4.ph.kcl.ac.uk> wrote:
>
> > I dont need to clean on an interrupt but some cleaning is needed when ever
any
> > pages are remapped due to having a virtual cache.
>
> Why not do the following for each page you remap:
>
> 1) Disable interupts
> 2) For each 32 byte potential data cache line within the page do an entry
> specific clean and flush
> 3) Remap the page, flush the data TLB entry
> 4) Enable interrupts
> 5) Check for any pending interrupts by calling the interrupt handler routine
> 6) Repeat for each page

If you were to use this scheme during a context switch then for fairly typical
large applications with 4MB of read-write mapped DRAM each you need to remap
roughly 1024 pages of 512 cache lines. Assuming that on average you can purge
10 cache lines every microsecond (not an unreasonable estimate) this means that
it takes you more than 50ms to purge a page. The standard BSD time-slice is
100ms so you could end up spending 50% of the CPU time in cache-flushing. For
applications with huge data areas (eg raytracers or X) the situation would be
much worse.

Cheers

Rob

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