Steve Woodford says;

> The vector table on older ARM CPUs was hard-wired to 0x0. This requires 
> some additional work on the part of the OS to ensure there is always a 
> valid kernel mapping at that address in every process, and to deal with 
> page faults if userland touches the vector page.

The fact, reset starts at address 0 and exception vector populated next
to it, is the weak point of ARM design.  What amused me is PDF says that
the reset value of V bit can be controlled by VINITHI strap, thus not for
the peace mind of SW constract.  This can not be a solution for the nature
of reset and runtime exception entry live in the same house. It's the point
I enphasis.

Toru Nishimura/ALKYL Technology