> >>I checked the ARM1026EJ-S TRM and it supports these same operations.  The 
> >>question is, does anyone know why NetBSD loops over all the sets/ways inste
> ad
> >> 
> >>of using the nifty operations?
> > 
> > 
> > That would be because the ARM1020E doesn't have those cache operations :-(
> > 
> > I thought I'd already added some support for the operations you mention, 
> > but I can't find it in my tree here.  Maybe it was at work.
> 
> Ah, so to use them, CPU_ARM10 would have to become smarter, or perhaps, 
> CPU_ARM10E would have to be added.

No, the ARM1020E, and ARM1022E (both arm10E cores) don't have these 
operations.  The ARM1026E does, as you've already mentioned, but all of 
these are CPU_ARM10E devices in reality (even though they are both called 
CPU_ARM10 in NetBSD.  Note the cache cleaning operations with opcode2=3 
are not documented in the v5 ARM ARM; I think they were late extensions, 
so in general you cannot rely on a core being able to do them.  There may 
be a way to tell if they are supported by querying other CP15 registers, 
but if there is, then I'm not aware of it.

Anyway, you don't have to handle this as a completely separate core, you 
just need to provide a suitable vector table.

R.