Danny Lau said;

> The chip(s3c2410) will raise an "Undefine instruction" exception(run time)

Isn't it possible to decode the failing instruction after all?
As you mentioned ARM instruction set is incompatible in frequently used
load/store manipulation.  It'd bring hard-to-believe mishaviours about memory
mapped I/O device registers which does care about load/store cycle and
sequence.  Your case differs, tough, since UNDEF exception is raised and
caught.

Toru Nishimura/ALKYL Technology