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I port NetBSD to an EP9315-based board.  And I want to some changes of
sys/arch/arm/ep93xx.

A. order priority of attaching device (attach.diff)
MAC address is stored in seeprom via GPIO(I^2C) on this board. I want
to find GPIO more before than epe0.

B. modify MDCDIV (mdcdiv.diff)
MDCDIV is fixed with 32 in epe.c.  I want to change it in config file.

C. write to PHY (phy.diff)
It is written with EP9315 manual in this way.
        (omitted 1-3)
        4. Put the PHY data into the PHY Data register
        5. Issue the write command to write data to the register with
          the PHY
        6. Wait until the write command is completed. Determine this
          by polling the MIIStatus_Busy Bit in MIIStatus Register.
I think current code is 5->4->6. It doesn't work on this board.

dmesg output is follows.

total memory = 65536 KB
avail memory = 60764 KB
mainbus0 (root)
cpu0 at mainbus0: ARM920T rev 0 (ARM9TDMI core)
cpu0: DC enabled IC enabled WB enabled EABT
cpu0: 16KB/32B 64-way Instruction cache
cpu0: 16KB/32B 64-way write-back-locking-A Data cache
epsoc0 at mainbus0: Cirrus Logic EP93xx SoC rev E0
epsoc0: fclk 200.02 Mhz hclk 100.01 Mhz pclk 50.00 Mhz
epclk0 at epsoc0 addr 0x80810000-0x8081008f intr 4
epgpio0 at epsoc0 addr 0x80840000-0x808400cb intr 59
armadillo9iic0 at epsoc0
iic0 at armadillo9iic0: I2C bus
seeprom0 at iic0 addr 0x50: AT24Cxx EEPROM
ohci0 at epsoc0 addr 0x80020000-0x80020fff intr 56
epe0 at epsoc0 addr 0x80010000-0x8001ffff intr 39
epe0: MAC address 00:11:0c:02:05:c0
lxtphy0 at epe0 phy 0: LXT971/2 10/100 media interface, rev. 2
lxtphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
epcom0 at epsoc0 addr 0x808c0000-0x808c0fff intr 52
epcom0: console
epwdt0 at epsoc0 addr 0x80940000-0x80940007 intr 36
eppcic0 at epsoc0 addr 0x80080020-0x80080043 intr 49
pcmcia0 at eppcic0
ohci0: OHCI version 1.0
usb0 at ohci0: USB revision 1.0
uhub0 at usb0
uhub0: Cirrus Logic OHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub0: 3 ports with 3 removable, self powered
wdc0 at pcmcia0 function 0: <TOSHIBA THNCF016MAA , , , >
wdc0: i/o mapped mode
atabus0 at wdc0 channel 0
wd0 at atabus0 drive 0: <TOSHIBA THNCF016MAA>
wd0: drive supports 1-sector PIO transfers, LBA addressing
wd0: 15872 KB, 248 cyl, 4 head, 32 sec, 512 bytes/sect x 31744 sectors
boot device: <unknown>

--
HAMAJIMA Katsuomi


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Index: current/arch/arm/ep93xx/epsocvar.h
diff -u current/arch/arm/ep93xx/epsocvar.h:1.1.1.1 current/arch/arm/ep93xx/epsocvar.h:1.1.2.2
--- current/arch/arm/ep93xx/epsocvar.h:1.1.1.1	Sat Jan  1 11:51:01 2005
+++ current/arch/arm/ep93xx/epsocvar.h	Mon Jul 18 16:55:04 2005
@@ -58,6 +58,7 @@
 	bus_space_tag_t		sc_iot;
 	bus_space_handle_t	sc_ioh;
 	bus_dma_tag_t		sc_dmat;
+	int			sc_pri;		/* attaching device priority */
 };
 
 extern struct epsoc_softc *epsoc_sc;
Index: current/arch/arm/ep93xx/epsoc.c
diff -u current/arch/arm/ep93xx/epsoc.c:1.1.1.3 current/arch/arm/ep93xx/epsoc.c:1.1.2.4
--- current/arch/arm/ep93xx/epsoc.c:1.1.1.3	Sat Oct  8 14:41:46 2005
+++ current/arch/arm/ep93xx/epsoc.c	Sat Oct  8 15:05:26 2005
@@ -165,8 +165,10 @@
 	/*
 	 *  Attach each devices
 	 */
+	sc->sc_pri = 2;
+	config_search_ia(epsoc_search, self, "epsoc", NULL);
+	sc->sc_pri = 1;
 	config_search_ia(epsoc_search, self, "epsoc", NULL);
-	
 }
 
 int
@@ -187,7 +189,7 @@
 	sa.sa_hclk = sc->sc_hclk;
 	sa.sa_pclk = sc->sc_pclk;
 
-	if (config_match(parent, cf, &sa) > 0)
+	if (config_match(parent, cf, &sa) == sc->sc_pri)
 		config_attach(parent, cf, &sa, epsoc_print);
 
 	return (0);
Index: current/arch/arm/ep93xx/epe.c
diff -u current/arch/arm/ep93xx/epe.c:1.1.1.2 current/arch/arm/ep93xx/epe.c:1.1.2.6
--- current/arch/arm/ep93xx/epe.c:1.1.1.2	Mon Jan 31 01:52:20 2005
+++ current/arch/arm/ep93xx/epe.c	Mon Aug  8 00:28:33 2005
@@ -136,7 +140,7 @@
 static int
 epe_match(struct device *parent, struct cfdata *match, void *aux)
 {
-	return 2;
+	return 1;
 }
 
 static void

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Index: current/arch/arm/ep93xx/epe.c
diff -u current/arch/arm/ep93xx/epe.c:1.1.1.2 current/arch/arm/ep93xx/epe.c:1.1.2.6
--- current/arch/arm/ep93xx/epe.c:1.1.1.2	Mon Jan 31 01:52:20 2005
+++ current/arch/arm/ep93xx/epe.c	Mon Aug  8 00:28:33 2005
@@ -93,6 +93,10 @@
 #include <arm/ep93xx/epereg.h> 
 #include <arm/ep93xx/epevar.h> 
 
+#ifndef EPE_MDCDIV
+#define EPE_MDCDIV	32
+#endif
+
 #ifndef EPE_FAST
 #define EPE_FAST
 #endif
@@ -406,7 +410,7 @@
 	}
 
 	/* Divide HCLK by 32 for MDC clock */
-	EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(32)|SelfCtl_PSPRS));
+	EPE_WRITE(SelfCtl, (SelfCtl_MDCDIV(EPE_MDCDIV)|SelfCtl_PSPRS));
 
 	sc->sc_mii.mii_ifp = ifp;
 	sc->sc_mii.mii_readreg = epe_mii_readreg;

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Content-Disposition: inline; filename="phy.diff"

Index: current/arch/arm/ep93xx/epe.c
diff -u current/arch/arm/ep93xx/epe.c:1.1.1.2 current/arch/arm/ep93xx/epe.c:1.1.2.6
--- current/arch/arm/ep93xx/epe.c:1.1.1.2	Mon Jan 31 01:52:20 2005
+++ current/arch/arm/ep93xx/epe.c	Mon Aug  8 00:28:33 2005
@@ -500,8 +504,8 @@
 	sc = (struct epe_softc *)self;
 	d = EPE_READ(SelfCtl);
 	EPE_WRITE(SelfCtl, d & ~SelfCtl_PSPRS); /* no preamble suppress */
-	EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg));
 	EPE_WRITE(MIIData, val);
+	EPE_WRITE(MIICmd, (MIICmd_WRITE | (phy << 5) | reg));
 	while(EPE_READ(MIISts) & MIISts_BUSY);
 	EPE_WRITE(SelfCtl, d); /* restore old value */
 }

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