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On Jan 17, 2005, at 3:02 AM, Steve Woodford wrote:

>> Changes I made:
>>   * bypass most dmamap_sync() and use DMA_COHERENT mappings
>
> For descriptor memory, this is actually a good idea on non cache 
> coherent
> platforms anyway. Especially if individual descriptors are smaller than
> a cache line.

Some experiments performed by some folks a while ago seemed to show 
that, on Xscale, at least, buffered/non-cacheable was the best mode for 
device control data (descriptors).  Unfortunately, there's not a good 
way to describe that in the current bus_dma(9) API.  Eventually, I'd 
like to introduce a DMA_DMA_CDATA flag that can provide this hint to 
the back-end.

> If you examine the object code for routines such as ip_input() et al,
> you'll see why. Nearly all the important network data structures have
> __attribute__((__packed__)) qualifiers, which causes gcc to emit
> bytewise loads/stores for all such structure members on architectures,
> like ARM, which don't support misaligned accesses.

Yah, Jesse, please remove those __packed__ attributes and run your test 
again.

         -- Jason R. Thorpe <thorpej@shagadelic.org>


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