> The cache/TLB are not flushed when context switching between a userland 
> process and a kernel thread. The cache will be flushed only if switching 
> to another userland process. The TLB will be flushed if switching to a 
> different L1 page table.

That's the ARM feature which is acutely different from MIPS.  Being tagged
with virtual address, cache contents, in principle, can never survive across
context switch, address space swap between processes.  U->K control
transition upon exception or interrupt receipt requires no cache flush since
UVA and KVA co-exist inside lower and upper address ranges.  Context
switch itself does not require to flush cache as KVA is a single entity shared
across processes.  Cache flush can be deffered until user address return.  The
deffered cache flush optimization would be useful unless kernel touchs user
address space contents.

MIPS takes a famous software managed TLB update strategy.  Its ASID field
eliminates the necessity to flush the entire TLB for every address space switch.
It's as simple as write a new ASID value in TLBHi COP0 register.

In restrospective, ARM shows its origin, born to replace 6502 processor.  MMU
and cache have been emphasized less.  The spectacular failure of ARM8
indicates the designers are unaware of how to make CPU process-model OS
friendly with minimal transistor counts.  For To learn "processor origin
metality" I found the following document is a good reading;

http://www.broadcom.com/collateral/wp/SB-1_WP100-R.pdf 

Toru Nishimura/ALKYL Technology, NetBSD values your intellectual property.