> On Sun, 2 Nov 2003 00:33:25 +0100
> Reinoud Zandijk <reinoud@netbsd.org> wrote:
> 
> > Dear folks,
> > 
> > after the recent patches to allow for misaligned access, the kernel
> > panics on a Acorn32 RiscPC (ARM7) with an ne2000 podule. It tries to
> > read a 16 bit with `ldr r3, [r0, #0x0002]' (insw+0x30) in blockio.S
> > and gets a `Alignment Fault 1' trap and dies. It looks like it wants
> > to execute the `fastinsw' routine.
>  
> > Other functions in blockio.S have the same alignment problems. Could
> > anyone please take a look and fix it? (I haven't been following
> > port-arm that much lately)
> 
> Perhaps the fastest way for now is to remove the aligned optimised
> cases.
> 
> I also suspect that that code may not work correctly with big endian
> either, but I'm not sure.
> 
> I believe ldrh and strh could be used on arms with those instructions to
> speed up that code.


STRH cannot be used on any Acorn machine since a store that misses the 
cache goes straight to the memory system.

LDRH can be used only if it can be guaranteed that the page is marked 
cacheable (not true for user-space since a shared page may be NCB).

In either case, these instructions can only be used if it is a SA-only 
kernel.

R.