At Mon, 14 Jul 2003 22:50:08 +0100,
Richard Earnshaw wrote:
> It then enters the loop below that scans over hwpend bits.  While 
> processing the statclock interrupt the SPL is effectively raised to 
> IPL_STAT_CLOCK with
> 
> 		current_spl_level |= iq->iq_mask;
> 		oldirqstate = enable_interrupts(I32_bit);
> 
> Interrupts are then enabled and the statclock handler code is called:
> 
> 		for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
> 		     ih = TAILQ_NEXT(ih, ih_list)) {
> 			(void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
> 		}

I think all of lower priority interrupts should masked by ICU hardware
before handlers are invoked.  If they masked by hardware,
XXX_intr_dispatch is never called by lower interrupts, and the
following code become not needed.

> 		if (pcpl & ibit) {
> 			/*
> 			 * IRQ is masked; mark it as pending and check
> 			 * the next one.  Note: the IRQ is already disabled.
> 			 */
> 			ifpga_ipending |= ibit;
> 			continue;
> 		}

ixp12x0_intr_dispatch() in ixp12x0_intr.c does it.  It simply mask the
lower interrupts before calling handler and simply restore mask before
leaving intr_dispatch().  If lower interrupts are occurred during
handler running, ixp12x0_intr_dispatch() is immediately called when
mask is restored.

--
Naoto Shimazaki