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More experimentation.  I've replaced runs of STR and LDR with STM and
LDM, tweaking the register usage in copyin to make the runs longer.  The
diff's attached.

Same test as ever: dd if=/dev/zero of=/dev/null count=1024 bs=1024k

ARM610, 30 MHz, 4KB unified cache:
brini:  1073741824 bytes transferred in 206.649 secs (5195969 bytes/sec)
briggs: 1073741824 bytes transferred in 92.540 secs (11603002 bytes/sec)
bjh21:  1073741824 bytes transferred in 75.677 secs (14188482 bytes/sec)

ARM710a, 40 MHz, 8KB unified cache:
brini:  1073741824 bytes transferred in 148.135 secs (7248400 bytes/sec)
briggs: 1073741824 bytes transferred in 48.377 secs (22195295 bytes/sec)
bjh21:  1073741824 bytes transferred in 48.248 secs (22254639 bytes/sec)

SA-110, 233 MHz, 16KB I-cache, 16KB D-cache:
brini:  1073741824 bytes transferred in 50.537 secs (21246647 bytes/sec)
briggs: 1073741824 bytes transferred in 43.931 secs (24441552 bytes/sec)
bjh21:  1073741824 bytes transferred in 43.889 secs (24464941 bytes/sec)

So significantly better performance on the ARM610, and almost no change on
ARM710a and SA-110.

-- 
Ben Harris                                                   <bjh21@netbsd.org>
Portmaster, NetBSD/acorn26           <URL:http://www.netbsd.org/Ports/acorn26/>


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