> > IIRC, the SA will merge writes to a cacheable area anyway.
> 
> The document seems to imply that, our hw guy didn't see it happen
> though (I didn't ever trace the memory cycles).

There are all sorts of reasons why it might not happen: one of them is 
that byte writes won't be merged if you have configured the SA memory 
system in "compatibility" mode, which makes the memory system interface 
more "compatible" with previous ARM chips.

> 
> (I've found a copy of the ARM instruction set - but not the encoding -
> on a document on the ARM web site.)

There's more there than that.  Keep looking :-)

R.