Subject: Re: Using different cache modes for r/o vs r/w pages
To: None <>
From: Richard Earnshaw <>
List: port-arm
Date: 01/30/2002 12:08:05
> Have you looked at the modified-emulation code?  That makes pages 
> read-only, so presumably you will have to mess with the cache bits when 
> doing that.  Maybe also for the referenced-emulation code.

The commit message for an ARM pmap bug that I fixed a while back read:

 revision 1.29
 date: 2001/11/01 15:49:16;  author: rearnsha;  state: Exp;  lines: +53 -35
 When clearing the modified bit for modified emulation, don't turn
 caching on for a page just because we are clearing the writable bit in
 the PTE: this is incompatible with the way pmap_vac_me_harder works,
 and the code in the modified emulation handler doesn't know about
 recalculating the cachable attributes (nor should it, IMO).

Given your need to recalculate the cacheable bits here, the above approach 
may no-longer be the best.  It might be the case that we should now make 
the cacheability of a page based on the current PTE writable attribute 
rather than the UVM attributes for the page.