Subject: Re: arc JC94 does not boot after thorpej-mips-cache merge
To: Izumi Tsutsui <tsutsui@ceres.dti.ne.jp>
From: Jason R Thorpe <thorpej@wasabisystems.com>
List: port-arc
Date: 11/22/2001 11:50:53 
On Fri, Nov 23, 2001 at 04:24:15AM +0900, Izumi Tsutsui wrote:

 > >cpu0 at mainbus0: MIPS R4400 CPU (0x460) Rev. 6.0 with MIPS R4010 FPC Rev. 0.0
 > >cpu0: L1 cache: 16KB/32B instruction, 16KB/32B data, direct mapped
 > >cpu0: L2 cache: 1024KB/64B mixed, no snooping
 > 
 > so should we also have 32B/line L1 cache ops for r4k?

Yes.

-- 
        -- Jason R. Thorpe <thorpej@wasabisystems.com>