Izumi Tsutsui <tsutsui@ceres.dti.ne.jp> wrote;

> The register offsets defined in arcsiopreg.h are:
>
> #define	SIOP_SCNTL0	0x00	/* rw: SCSI control reg 0 */
> #define	SIOP_SCNTL1	0x01	/* rw: SCSI control reg 1 */
> #define	SIOP_SDID	0x02	/* rw: SCSI destination ID */
> #define	SIOP_SIEN	0x03	/* rw: SCSI interrupt enable */
>
> but in sys/arch/amiga/siopreg.h, they are:
>
> /*00*/  volatile unsigned char  siop_sien;	/* rw: SCSI Interrupt Enable */
> /*01*/  volatile unsigned char  siop_sdid;	/* rw: SCSI Destination ID */
> /*02*/  volatile unsigned char  siop_scntl1;	/* rw: SCSI control reg 1 */
> /*03*/  volatile unsigned char  siop_scntl0;	/* rw: SCSI control reg 0 */
>
> Anyway, we need re-think how to handle these endianness. Umm..

Tik-tik-tik.  Hacking CISCy device driver into RISCy one would bring
mess at best.  It's a very common issue to share single device driver
source code between CISCy and RISCy.  Look at the LANCE, Z85C30 or
fl(u)ppy everything.  Smart hardwares need smart drivers.  If things
can not be written in sane, it's a hardware designer's fault.  (I have
Vr4100 evaluation board documentation to tell chip registers populated
in 64bit strides)  In retrospective, MI ncr53cxx driver settled in a
moderate solution.

Tohru Nishimura