On Sat, Feb 10, 2001 at 09:51:29PM -0700, Warner Losh wrote:
> In message <20010210234622.B1040@mail.radicalmedia.com> Mark Abene writes:
> : Could you elaborate on your kludge?  What needed to be fixed exactly?
> : Was the cache coherency problem with L2 cache?
> 
> cache invalidation before/after dma, at least for the affected address
> range.  I think that busdma does the right thing now.  IT was for L1
> cache in my case, but L2 cache that the cpu manages might be the
> problem and you might not be flushing properly.  Or maybe you are and
> the problem lies elsewhere.  I had a vr4102 based machine that hung in
> init for one version, but a version 3 months later worked great.
> There was a small chance it was build environment, so maybe that's
> biting you.  The Linux/mips people like to say how buggy the mips code
> generation is with binutils.
> 
> Warner

I'll recheck the L2 cache code in locore_mips3.S, since I had to make changes
there to allow for the Magnum SC's 16-byte line size.  You mention there was
a driver you had to kludge... which driver was it?
I'd be hesitant to think the cross/mipsel toolchain is at fault, since plenty
of other people are using it on this list, and the pica and olivetti people
seem perfectly fine at last check (though the pica code doesn't use the L2
cache, and the olivetti doesn't have one).
I still find it suspicious that I panic with "TLB out of universe" if I try
disabling the L2 cache code.  The panic happens when init is about to start.

-Mark