Subject: Re: MIPS Magnum 4000-PC fails to boot
To: Jason R Thorpe <thorpej@zembu.com>
From: Mark Abene <phiber@radicalmedia.com>
List: port-arc
Date: 11/11/2000 07:54:04
On Fri, Nov 10, 2000 at 06:53:22PM -0800, Jason R Thorpe wrote:
> 
> Okay, with this change I'm in single-user mode now.  And, I'm a little
> puzzled:
> 
> # 
> # 
> # ls
> .cshrc    altroot   dev       home      root      stand     usr
> .profile  bin       etc       mnt       sbin      tmp       var
> # date
> Fri Nov 10 10:50:50 PST 2000
> # ls /usr
> bin     include libdata lkm     mdec    share
> games   lib     libexec local   sbin
> # date
> Fri Nov 10 10:50:54 PST 2000
> # 
> 
> ...okay, the time has advanced... So, are we or are we not blocking
> the clock interrupts?!

We're blocking *interval timer* interrupts, which the MCT ADR signals to the
cpu on INT4.  The RTC has nothing to do with the interval timer.  The RTC is
provided by an mc146818-compatible Dallas DS1287.  So the time is unaffected
by our problem.  The DS1287, as well as other "local bus" (on-board) devices,
have various resources controlled by the MCT ADR, which all share INT0.
When you get an INT0, you check the local bus interrupt source register at
0xe0040000, which clears the pending INT0, and gives you a bit mask of which
local bus device has interrupted (ether, rtc, serial, etc., etc.), based on
what was allowed in the interrupt enable register at 0xe0040002.  See picabus.c:
pica_iointr() and pica.h for details.  Anyway, we're actually concerned with
pica_clkintr() which is the INT4 interval timer interrupt handler, which is
supposed to be clearing pending interrupts (but it's not).  It *does* work on
the Acer Pica and Olivetti, but not on the Magnum.  The interval timer is being
used for the 100Hz "jiffy" timer, which e.g. device drivers use for delay
counters and such.
You know what a jiffy clock is for, so I won't insult your intelligence.  :)
The RTC's highest resolution is whole seconds, so it isn't a candidate for
being used as a jiffy clock.  We basically had two choices: use the MCT ADR's
interval timer, or use the R4000's on-chip counter/compare timer (which uses
INT5).  NetBSD and Linux chose to use the interval timer.  RISC/OS chose to
use the on-cpu timer, for reasons we don't know.  NetBSD has ifdefs for the
on-cpu timer, but not as a jiffy clock; rather as a cpu performance counter.
If we found out for some reason that the MCT ADR interval timer wasn't usable
on the Magnum, we'd probably have to rewrite the kernel to use the cpu timer
for the jiffy clock instead, as that would be our only other choice.
Which is why we need Magnum docs, to know one way or the other.  :)

> 
> Sorry, the ARC port is spaghetti to me right now (maybe I'll spend
> some time and make it more Alpha port like :-), so I might just be
> missing something......
> 
> -- 
>         -- Jason R. Thorpe <thorpej@zembu.com>

I hope I explained the situation to your liking.  :)

Cheers,
-Mark