On Thu, Nov 09, 2000 at 10:56:51AM -0800, Jason R Thorpe wrote:
> 
> Okay, here you go:
[...]
> ABOUT TO _splnone
> [ ....WEDGE.... ]
> 

OK, do me a favor.  In arch/mips/mips/locore.S, find _splnone, and change:

        li      v0, (MIPS_INT_MASK | MIPS_SR_INT_IE)

to read:

        li      v0, ((MIPS_INT_MASK & ~MIPS_INT_MASK_4)| MIPS_SR_INT_IE)

If this gets you past _splnone(), then we have ourselves a winner.  Same 
problem on *both* Magnums, PC AND SC.  Which blows away my theory.  My theory
was that since the R4000SC only has one interrupt pin (INT0), and the PC
has 6, I was thinking that maybe external interrupts via the transparent
interrupt register had to be cleared differently as the INT4 from the R4030
doesn't have a dedicated cpu pin on the R4000SC.  I was basing this on the
fact that the Olivetti M700 is supposed to be a clone of the Magnum 4000PC,
both of which use an R4230 MCT ADR.  The Olivetti doesn't suffer from the
problem we're seeing, and the interval timer works just fine.  I just had
a look at the Olivetti's ARC firmware.  It's different from the Magnum's,
but so far I don't see it doing anything out of the ordinary with the
interval timer registers.
There's also the fact that neither the RISC/OS firmware nor the RISC/OS kernel
make use of the interval timer.  They chose to use the on-cpu timer for their
clock interrupts.  Maybe they had good reason?  Maybe the R4030/4230 isn't
wired up properly on the Magnum?  Or maybe ARC isn't initializing the ASIC
to our satisfaction?  We really need to locate the tech manual for the Magnum,
which hopefully describes the interrupt mappings, and whether the ASIC's
interval timer->INT4 setup isn't totally broken...

Let me know what happens.  Also, there's no chance you actually have a 4000SC
motherboard in a 4000PC chassis, is there?  Could you check?  I know it's
silly, but I want to be sure.  Also, if you could verify that you have a 4230
in your machine.

Thanks!
-Mark