On Tue, Oct 10, 2000 at 11:41:23AM +0900, Noriyuki Soda wrote:
> > Exactly.  This is a strong possibility right now.  Do you have any way of
> > verifying the technical specs?
> 
> I cannot access the technical specs at least until this weekend,
> since I'm in the middle of a business trip now.
> Also, I have vague memory that the specs only describes the behaviour
> of the currently coded case of the R4030_SYS_IT_STAT.
> --
> soda
> 

In looking at the R4000 user's manual pdf from mips.com, we find the following:

Chapter 15
402 MIPS R4000 Microprocessor User's Manual
15.1 Hardware Interrupts
The six CPU hardware interrupts can be caused by external write requests
to the R4000SC, R4000MC, and R4000PC, or can be caused through
dedicated interrupt pins. These pins are latched into an internal register
by the rising edge of SClock. The R4000MC and R4000SC packages
support a single interrupt pin, Int*(0). The R4000PC package supports six
interrupt pins, Int*(5:0).

Is the interval timer, which we assume is interrupting on INT4, an "external
write request"?  I ask because I understand from this description that there
is no actual INT4 pin on a 4000SC.
It would at least appear that we *are* getting INT4 requests, because if I
modify _splnone() to enable all interrupts EXCEPT INT4, the kernel no longer
hangs at _splnone() and actually proceeds to root device selection as expected.

Without having more specs on the function of the IT_VALUE and IT_STAT registers
and their behavior on the 4000SC, I'm stuck at the moment.  Maki and myself
have already devoted quite a bit of time in experimentation, but at this point
I think it all boils down to needing more information to get this working.

Any info anyone can provide would be more than welcome!

Cheers,
-Mark