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On Fri, Sep 14, 2001 at 12:00:54AM +0100, Lars Hecking wrote:
>  
> > > You didn't mention your serial speed setting. Try to make it small, say
> > > 19200 bps, and see if you get better througput. THis will give us a hint as to
> > > what to look for.
> > 
> >  I'm 99% certain the setting is 38400.
>  
>  Indeed. Lowering it to 19200 makes no noticeable difference.

Hm. 

I checked the chip docs, and as far as I can tell, the DMA bursts themselves
are limited to (at most) 16 cycles, with 5 cycles for oter bus masters (e.g.
the CPU) in between. So the DMA itself isn't the culprit.

However - the dma_cachectl() kernel function called before DMA and the
cachectl() used by the VM system will use 
a page-sized flush instruction for long enough transfers. For 38400, this
may well lock out the cpu long enough to lose characters, for 19200 it
depends on memory speed (the Motorola numbers in the User Manual are for
2-1-1-1 cpu burst cycles, which is pretty fast - at A3000 fastmem
is 5-2-2-2 for static column chips, else 5-5-5-5.

So at least if you still are using your mainboard memory, you're in trouble.

Please apply the appended patch to sys_machdep.c. It will force the mentioned
functions to always use line-sized flushes.

Regards,
	-is


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--- sys_machdep.c.back	Mon Sep 17 21:57:01 2001
+++ sys_machdep.c	Mon Sep 17 22:15:04 2001
@@ -79,16 +79,15 @@
 		if (addr == 0 ||
 #if defined(M68040)
 #if defined(M68060)
-		    (cputype == CPU_68040 && req & CC_IPURGE) ||
+		    (cputype == CPU_68040 && req & CC_IPURGE))
 #else
-		    (req & CC_IPURGE) ||
+		    (req & CC_IPURGE))
 #endif
 #endif
-		    ((req & ~CC_EXTPURGE) != CC_PURGE && len > 2*NBPG))
 			doall = 1;
 		if (!doall) {
 			end = addr + len;
-			if (len <= 1024) {
+			if (1) {
 				addr = addr & ~0xF;
 				inc = 16;
 			} else {
@@ -193,7 +192,7 @@
 		caddr_t end;
 
 		end = addr + len;
-		if (len <= 1024) {
+		if (1) {
 			addr = (caddr_t)((int)addr & ~0xF);
 			inc = 16;
 		} else {

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