On Fri, Apr 17, 1998 at 09:12:18PM -0600, Michael L. Hitch wrote:
>   The block limits seem rather strange - I'd suspect they are probably
> garbage.  The buffer for the block limits doesn't appear to be cleared
> and the actual length of the data returned doesn't appear to be checked,
> so it's possible that those values are garbage left on the stack.  More
> likely, the buffer is not on a long word boundary and is six bytes long,
> and I suspect the driver is not getting the DMA data transferred properly.

This is highly probable.

As far as I know, the DMA hardware of the Fastlane uses an internal fifo which
is automatically cleared on each setup.

So it is not possible to correctly transfer odd-sized blocks to unaligned
buffers doing multi-segment magic... you have to poll them, or bounce buffer
the WHOLE transfer.

Other P5 boards dont have this limitations.

Regards,
	Ignatios