Hello,
here is a patch to implement initial PCID support for amd64. This feature is available on recent Intel processors, starting with Haswell, and optimises TLB use during address space switch.
The patch compiles and seems to work fine in emulator, but I haven't tested it with real hardware just yet. I should be able to do so in a week or so. By then I'd also see if there is any performance improvement. I'm sharing this now just to gather some early feedback.
It only activates when both PCID and INVPCID is supported by boot processor. I think it's not worth the efford any more to try supporting the early machines with PCID but without INVPCID.
I've considered using the MI pmap_tlb.c ASID code and evaluated sparc64 CTX and alpha ASN counterparts. Opted to use sparc64 pmap approach for simplicity and similar features (12 bits context space compared to sparc 13+), on the end I however actually used pretty much the alpha approach. It's using just a generation number for invalidation on ASID wraparound, instead of an explicit pmap list like sparc64.
There is no support for SVS yet, which was actually the primary driver for this effort. SVS code will need to be modified to not force TLB flushes on address space switch. This will be now the next step for me.
Thoughts welcome. I plan to integrate this into the -current tree within couple of weeks.
Jaromir