On Wed, Jan 17, 2001 at 11:57:01PM +0100, Olaf Seibert wrote:
> On Wed 17 Jan 2001 at 22:03:25 +0100, Wilko Bulte wrote:
> > On Wed, Jan 17, 2001 at 09:54:55PM +0100, Olaf Seibert wrote:
> > > It seems that even in 1.5 the Pyxis DMA workaround is not perfect yet.
> > > I was careful to try the netbsd.ram kernel, and it did not work properly
> > 
> > There are multiple ECO levels on the MX5 so you might have hardware that is
> > not up to the latest rev. Just a guess of course

You could send me your revision level of the MLB. I might be able to check
how 'old' as far as ECOs go, your board  is.

> That is of course quite possible.
> 
> When browsing through the source, I found the following comment a bit
> suspicious:
> 
> /*
>  * Flush the scatter/gather TLB on broken Pyxis chips.
>  */
> void
> cia_broken_pyxis_tlb_invalidate()
> {
> ......
>         /*
>          * Now, read from PCI dense memory space at offset 128M (our
>          * target window base), skipping 64k on each read.  This forces
>          * S/G TLB misses.
>          *
>          * XXX Looks like the TLB entries are `not quite LRU'.  We need
>          * XXX to read more times than there are actual tags!
>          */
>  
> in arch/alpha/pci/cia_dma.c. A thing like this sounds like it could differ
> between revisions - maybe my version needs still more forced TLB misses?
> Or am I talking nonsense here?

Sorry, I do not know enough of the intricacies involved here to really
comment with useful information.

W/
-- 
|   / o / /  _  	 Arnhem, The Netherlands    	email: wilko@freebsd.org
|/|/ / / /( (_) Bulte	 http://www.freebsd.org 	http://www.nlfug.nl