Jason R Thorpe <thorpej@zembu.com> writes:
> Thankfully, DEC hardware has a sleazy hack that allows you do avoid
> this song-and-dance ... and the `zs' (and `scc') driver already does
> it.
> 
> Alpha and DECstation are little-endian, and the bytes happen to be
> padded out.  So, do 4-byte access with the byte you want in the least
> significant 8-bits of the 4-byte longword.

i dunno what the code does (and it's too late for any understanding),
but i suppose it follows this description, and this description is
incorrect (and unfairly maligns the hardware design 8-).

If ek-d3sys-pm is to be believed (and it's the bible by which I did
the port to begin with 8-), then, as i mentioned to you earlier:

page 9-13: "The ISDN registers, like the SCC registers, are
longword-aligned; data is read from and written to byte 1."

and went on to explain: what that actually meant in terms of register
values.  to quote page 9-11:

	The SCC registers are aligned to longwords with data being
	read and written from byte 1.  For example, writing a
	0x01234567 to an SCC register sets it to a value of 45.
	Reading a register with a value of 45 will return xxxx45xx,
	where x = UNPREDICTABLE data.

note that the alpha IOASIC zs attachment code
(arch/alpha/tc/zs_ioasic.c) implements this in the read and write reg
functions.  to pase from read_reg:

        *((volatile unsigned int *) cs->cs_reg_csr) =
            ((volatile unsigned int) reg) << 8;
        tc_mb();
        DELAY(5);

        val = ((*(volatile unsigned int *) cs->cs_reg_csr) >> 8) &
        0xff;
        tc_mb();
        DELAY(5);

i'd expect that the alpha code for the bba should do the same thing,
and further i'd expect that bus_space_*_4 won't do it.  8-)


cgd
-- 
Chris Demetriou - cgd@netbsd.org - http://www.netbsd.org/People/Pages/cgd.html
Disclaimer: Not speaking for NetBSD, just expressing my own opinion.