On Thu, Mar 16, 2000 at 03:08:51PM +0100, Frank van der Linden wrote:
> Can't help you with the internals of the alpha pci memory space mappings,
> but.. perhaps you can try adding a few lines of code to fall back to
> I/O space if memory space fails (like most other PCI driver frontends do).

Drivers do this for boards which provides 2 Base address register, one
for I/O and one for mem. It seems the netgear doesn't do this, from the
output of pci_conf_print():
ti0 at pci0 dev 8 function 0PCI configuration registers:
  Common header:
    0x00: 0x620a1385 0x02a00006 0x02000001 0x0000f810

    Vendor Name: Netgear (0x1385)
    Device Name: GA620 Gigabit Ethernet (0x620a)
    Command register: 0x0006
      I/O space accesses: off
      Memory space accesses: on
      Bus mastering: on
      Special cycles: off
      MWI transactions: off
      Palette snooping: off
      Parity error checking: off
      Address/data stepping: off
      System error (SERR): off
      Fast back-to-back transactions: off
    Status register: 0x02a0
      Capability List support: off
      66 MHz capable: on
      User Definable Features (UDF) support: off
      Fast back-to-back capable: on
      Data parity error detected: off
      DEVSEL timing: medium (0x1)
      Slave signaled Target Abort: off
      Master received Target Abort: off
      Master received Master Abort: off
      Asserted System Error (SERR): off
      Parity error detected: off
    Class Name: network (0x02)
    Subclass Name: ethernet (0x00)
    Interface: 0x00
    Revision ID: 0x01
    BIST: 0x00
    Header Type: 0x00 (0x00)
    Latency Timer: 0xf8
    Cache Line Size: 0x10

  Type 0 ("normal" device) header:
    0x10: 0x01020000 0x00000000 0x00000000 0x00000000
    0x20: 0x00000000 0x00000000 0x00000000 0x00011385
    0x30: 0x00000000 0x00000000 0x00000000 0x0040011b

    Base address register at 0x10
      type: 32-bit nonprefetchable memory
      base: 0x01020000, size: 0x00004000
    Base address register at 0x14
      not implemented(?)
    Base address register at 0x18
      not implemented(?)
    Base address register at 0x1c
      not implemented(?)
    Base address register at 0x20
      not implemented(?)
    Base address register at 0x24
      not implemented(?)
    Cardbus CIS Pointer: 0x00000000
    Subsystem vendor ID: 0x1385
    Subsystem ID: 0x0001
    Expansion ROM Base Address: 0x00000000
    Reserved @ 0x34: 0x00000000
    Reserved @ 0x38: 0x00000000
    Maximum Latency: 0x00
    Minimum Grant: 0x40
    Interrupt pin: 0x01 (pin A)
    Interrupt line: 0x1b


--
Manuel Bouyer, LIP6, Universite Paris VI.           Manuel.Bouyer@lip6.fr
--