[ Not speaking for DEC, yadda yadda. ]

> Well, assuming the manufacturer had set that bit.  The board (or at
> least most of the software they provide) depends on linear access,

"The software wasn't necessarily meant to work on the Alpha."

That bit determines whether or not PCI memory is prefetchable,
whether writes to that space can be merged, and has some other
semantics.  If the bit is set, i.e. the memory is marked as
prefetchable, it can be prefetched, reads are assumed to have no
side-effects, and writes can be merged.  That corresponds to the
semantics provided by dense space.  If the bit is not set, those
things cannot be done, and use of the space has the features provided
by sparse space.

At least on many alphas, there's no such thing as non-prefetchable,
non-write-merging linear access to device space.  Trying to use dense
space on devices which aren't supposed to be prefetchable and/or which
can't have writes collapsed _WILL_ lose in some circumstances, and
will be a royal PITA for you to debug.

I can't prevent you from doing it, but if you're faced with a serious
debugging headache (the driver might be mostly working, and fail in
some very hard-to-reproduce situation, for instance), "I told you so."
8-)

</rant>


> I
> went & looked at the econfig space for a myrinet board (0x804310E8) and
> for the TGA (0x00041011, to see what it should look like).
>
> 	>>>e -l -n 4 econfig:C0000
> 	econfig:            C0000 804310E8 
> 	econfig:            C0004 04000046 
> 	econfig:            C0008 00000001 
> 	econfig:            C000C 0000FF00 
> 	econfig:            C0010 82000000 
> 	>>>e -l -n 4 econfig:B0000 
> 	econfig:            B0000 00041011 
> 	econfig:            B0004 02800087 
> 	econfig:            B0008 03800002 
> 	econfig:            B000C 0000FF00 
> 	econfig:            B0010 88000008 
> 
> So, in order to specify that the board needs linear access, you're
> saying that 0xC0010 should be '0x88000008' like it is in the TGA,
> right? 

What really matters is the low 4 bits (for memory mapping registers):

>From pcireg.h:

#define PCI_MAPREG_TYPE_MASK                    0x00000001

#define PCI_MAPREG_TYPE_MEM                     0x00000000
#define PCI_MAPREG_TYPE_IO                      0x00000001


#define PCI_MAPREG_MEM_TYPE_MASK                0x00000006

#define PCI_MAPREG_MEM_TYPE_32BIT               0x00000000
#define PCI_MAPREG_MEM_TYPE_32BIT_1M            0x00000002
#define PCI_MAPREG_MEM_TYPE_64BIT               0x00000004


#define PCI_MAPREG_MEM_CACHEABLE_MASK           0x00000008

(That last is a misnomer.)


The rest is the PCI address where that region lives.  For the myrinet
board, if they wanted the region to be cacheable/prefetchable, they
would have set the 0x08 bit of the 0xc0010 config space register, yes.



cgd