Subject: Re: Xarm32VIDC from 1.6.1 very unstable
To: Frank Wennmohs <frankw@bph.ruhr-uni-bochum.de>
From: Richard Earnshaw <rearnsha@buzzard.freeserve.co.uk>
List: port-acorn32
Date: 08/26/2003 00:44:31
This is a multipart MIME message.

--==_Exmh_5678573740
Content-Type: text/plain; charset=us-ascii


frankw@bph.ruhr-uni-bochum.de said:
> xwininfo: Window id: 0x2a (the root window) (has no name)
>   Absolute upper-left X:  0
>   Absolute upper-left Y:  0
>   Relative upper-left X:  0
>   Relative upper-left Y:  0
>   Width: 1024
>   Height: 768
>   Depth: 8
>   Visual Class: PseudoColor 

Seems alright for me with an Xserver built with a version of GCC that has 
this patch applied.  Can you give this a whirl..

Apply the attached patch to /usr/src/gnu/dist/toolchain/gcc/config/arm/arm.
c
Rebuild cc1 and install it.
Rebuild your X server and install it.

R.

--==_Exmh_5678573740
Content-Type: text/plain ; name="arm-reload.patch"; charset=us-ascii
Content-Description: arm-reload.patch
Content-Disposition: attachment; filename="arm-reload.patch"

Index: arm.c
===================================================================
RCS file: /cvsroot/src/gnu/dist/toolchain/gcc/config/arm/arm.c,v
retrieving revision 1.11
diff -p -p -r1.11 arm.c
*** arm.c	2003/05/23 00:20:21	1.11
--- arm.c	2003/08/25 23:39:23
*************** arm_reload_in_hi (operands)
*** 3770,3778 ****
       rtx *operands;
  {
    rtx ref = operands[1];
!   rtx base, scratch;
    HOST_WIDE_INT offset = 0;
  
    if (GET_CODE (ref) == SUBREG)
      {
        offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
--- 3770,3781 ----
       rtx *operands;
  {
    rtx ref = operands[1];
!   rtx base, scratch, scratch2;
    HOST_WIDE_INT offset = 0;
  
+   scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
+   scratch2 = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
+ 
    if (GET_CODE (ref) == SUBREG)
      {
        offset = SUBREG_WORD (ref) * UNITS_PER_WORD;
*************** arm_reload_in_hi (operands)
*** 3805,3811 ****
    if (GET_CODE (base) == MINUS
        || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
      {
!       rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
  
        emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
        base = base_plus;
--- 3808,3814 ----
    if (GET_CODE (base) == MINUS
        || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT))
      {
!       rtx base_plus = scratch;
  
        emit_insn (gen_rtx_SET (VOIDmode, base_plus, base));
        base = base_plus;
*************** arm_reload_in_hi (operands)
*** 3839,3845 ****
  
        if (hi != 0)
  	{
! 	  rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
  
  	  /* Get the base address; addsi3 knows how to handle constants
  	     that require more than one insn */
--- 3842,3848 ----
  
        if (hi != 0)
  	{
! 	  rtx base_plus = scratch;
  
  	  /* Get the base address; addsi3 knows how to handle constants
  	     that require more than one insn */
*************** arm_reload_in_hi (operands)
*** 3849,3885 ****
  	}
      }
  
!   /* Operands[2] may overlap operands[0] (though it won't overlap
!      operands[1]), that's why we asked for a DImode reg -- so we can
!      use the bit that does not overlap.  */
!   if (REGNO (operands[2]) == REGNO (operands[0]))
!     scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
!   else
!     scratch = gen_rtx_REG (SImode, REGNO (operands[2]));
  
!   emit_insn (gen_zero_extendqisi2 (scratch,
  				   gen_rtx_MEM (QImode,
  						plus_constant (base,
  							       offset))));
!   emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0),
  				   gen_rtx_MEM (QImode, 
  						plus_constant (base,
  							       offset + 1))));
!   if (! BYTES_BIG_ENDIAN)
      emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
- 			gen_rtx_IOR (SImode, 
- 				     gen_rtx_ASHIFT
- 				     (SImode,
- 				      gen_rtx_SUBREG (SImode, operands[0], 0),
- 				      GEN_INT (8)),
- 				     scratch)));
-   else
-     emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
  			    gen_rtx_IOR (SImode, 
! 					 gen_rtx_ASHIFT (SImode, scratch,
  							 GEN_INT (8)),
! 					 gen_rtx_SUBREG (SImode, operands[0],
! 							 0))));
  }
  
  /* Handle storing a half-word to memory during reload by synthesising as two
--- 3852,3889 ----
  	}
      }
  
!   if (GET_CODE (base) != REG)
!     abort ();
  
!   /* Operands[2] may overlap BASE.  Ensure that we don't clobber it in
!      the first load.  */
!   if (REGNO (scratch2) == REGNO (base))
!     {
!       rtx tmp = scratch2;
!       scratch2 = scratch;
!       scratch = tmp;
!     }
! 
!   emit_insn (gen_zero_extendqisi2 (scratch2,
  				   gen_rtx_MEM (QImode,
  						plus_constant (base,
  							       offset))));
!   emit_insn (gen_zero_extendqisi2 (scratch,
  				   gen_rtx_MEM (QImode, 
  						plus_constant (base,
  							       offset + 1))));
!   if (BYTES_BIG_ENDIAN)
      emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
  			    gen_rtx_IOR (SImode, 
! 					 gen_rtx_ASHIFT (SImode, scratch2,
  							 GEN_INT (8)),
! 					 scratch)));
!   else
!     emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0),
! 			gen_rtx_IOR (SImode, 
! 				     gen_rtx_ASHIFT (SImode, scratch,
! 						     GEN_INT (8)),
! 				     scratch2)));
  }
  
  /* Handle storing a half-word to memory during reload by synthesising as two

--==_Exmh_5678573740--