Hiya Mike,

On Fri, Feb 01, 2002 at 06:52:58PM +0000, Mike Pumford wrote:
> The wscons code will need some work before it is sane on StrongARM RiscPCs.
> It needs to do cache flushes at some points or there is noticable (about half 
> a second lag) on the screen updates. Its also really bad at boot time as it 
> takes even longer before stuff appears on the screen. I am quite willing to 
> compile test patches for this but I don't understand wscons enough to generate 
> the required fixes myself. 

Oh ! I wasn't aware of this having a ARM7 RiscPC here... hmm... yeah i'll
look at the situation and i think i've got a good idea how to solve it : if
something is printed, a counter might be increased and checked with a
configurable maximum. This counter is then decreased in the VSYNC interrupt
and when it reaches zero it can make sure that the data cache in that
memory area is flushed. The configuration can be tweaked so ppl say want at 
most a 20 times a sec or so updates and not every one ... or want say every 
vsync a flush or whatever.... 

Thanks for the tip,
Reinoud