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u-boot-licheepi-zero: add package for testing RGB panel
Module Name: pkgsrc-wip
Committed By: Rui-Xiang Guo <rxg%lavabit.com@localhost>
Pushed By: rxg
Date: Fri Feb 27 11:00:03 2026 +0800
Changeset: 34eb2fdc306ddcaee6f33725ba4176bc7c1f2bd1
Modified Files:
Makefile
Added Files:
u-boot-licheepi-zero/DESCR
u-boot-licheepi-zero/Makefile
u-boot-licheepi-zero/PLIST
u-boot-licheepi-zero/files/installboot.plist
u-boot-licheepi-zero/files/sun8i-v3s-licheepi-zero-lcd-480x272.dts
u-boot-licheepi-zero/files/sun8i-v3s-licheepi-zero-lcd-800x480.dts
u-boot-licheepi-zero/patches/patch-arch_arm_dts_sun8i-v3s-licheepi-zero.dts
u-boot-licheepi-zero/patches/patch-arch_arm_dts_sun8i-v3s.dtsi
u-boot-licheepi-zero/patches/patch-arch_arm_include_asm_arch-sunxi_clock__sun6i.h
u-boot-licheepi-zero/patches/patch-arch_arm_include_asm_arch-sunxi_gpio.h
u-boot-licheepi-zero/patches/patch-arch_arm_mach-sunxi_Kconfig
u-boot-licheepi-zero/patches/patch-drivers_pwm_sunxi__pwm.c
u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_lcdc.c
u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__de2.c
u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__dw__hdmi.c
u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__lcd.c
u-boot-licheepi-zero/patches/patch-include_configs_sunxi-common.h
Log Message:
u-boot-licheepi-zero: add package for testing RGB panel
The patches mainly come from
https://github.com/u-boot/u-boot/compare/master...mcerveny:u-boot:simplefb_v3s_v2
To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=34eb2fdc306ddcaee6f33725ba4176bc7c1f2bd1
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
diffstat:
Makefile | 1 +
u-boot-licheepi-zero/DESCR | 5 +
u-boot-licheepi-zero/Makefile | 21 ++
u-boot-licheepi-zero/PLIST | 3 +
u-boot-licheepi-zero/files/installboot.plist | 47 +++
.../files/sun8i-v3s-licheepi-zero-lcd-480x272.dts | 38 ++
.../files/sun8i-v3s-licheepi-zero-lcd-800x480.dts | 43 +++
.../patch-arch_arm_dts_sun8i-v3s-licheepi-zero.dts | 110 ++++++
.../patches/patch-arch_arm_dts_sun8i-v3s.dtsi | 399 +++++++++++++++++++++
...-arch_arm_include_asm_arch-sunxi_clock__sun6i.h | 30 ++
.../patch-arch_arm_include_asm_arch-sunxi_gpio.h | 12 +
.../patches/patch-arch_arm_mach-sunxi_Kconfig | 12 +
.../patches/patch-drivers_pwm_sunxi__pwm.c | 12 +
.../patches/patch-drivers_video_sunxi_lcdc.c | 30 ++
.../patches/patch-drivers_video_sunxi_sunxi__de2.c | 66 ++++
.../patch-drivers_video_sunxi_sunxi__dw__hdmi.c | 13 +
.../patches/patch-drivers_video_sunxi_sunxi__lcd.c | 27 ++
.../patches/patch-include_configs_sunxi-common.h | 16 +
18 files changed, 885 insertions(+)
diffs:
diff --git a/Makefile b/Makefile
index 669ba43ed1..e3bb4c1d26 100644
--- a/Makefile
+++ b/Makefile
@@ -5877,6 +5877,7 @@ SUBDIR+= u-boot
SUBDIR+= u-boot-full
SUBDIR+= u-boot-imx23-olinuxino
SUBDIR+= u-boot-khadas-vim3
+SUBDIR+= u-boot-licheepi-zero
SUBDIR+= u-boot-mangopi-mq-pro
SUBDIR+= u-boot-nanopi-r2s
SUBDIR+= u-boot-omap4-panda
diff --git a/u-boot-licheepi-zero/DESCR b/u-boot-licheepi-zero/DESCR
new file mode 100644
index 0000000000..0b4d150d3e
--- /dev/null
+++ b/u-boot-licheepi-zero/DESCR
@@ -0,0 +1,5 @@
+U-Boot is a bootloader for embedded boards based on PowerPC, ARM, MIPS and
+several other processors, which can be installed in a boot ROM and used to
+initialize and test the hardware or to download and run application code.
+
+This package provides U-Boot for the Lichee Pi Zero.
diff --git a/u-boot-licheepi-zero/Makefile b/u-boot-licheepi-zero/Makefile
new file mode 100644
index 0000000000..6054df2f35
--- /dev/null
+++ b/u-boot-licheepi-zero/Makefile
@@ -0,0 +1,21 @@
+# $NetBSD: Makefile,v 1.2 2021/08/12 07:25:57 wiz Exp $
+
+UBOOT_TARGET= licheepi-zero
+UBOOT_CONFIG= LicheePi_Zero_defconfig
+UBOOT_BIN= u-boot-sunxi-with-spl.bin
+UBOOT_LCD_MODE= 800x480 # or 480x272
+
+UBOOT_INSTALLBOOT_PLIST= installboot.plist
+
+post-patch:
+ cd ${WRKSRC}; \
+ for f in ${.CURDIR}/patches/patch-*; do \
+ ${PATCH} -p0 < $$f; \
+ done
+ ${CP} ${FILESDIR}/sun8i-v3s-licheepi-zero-lcd-${UBOOT_LCD_MODE}.dts ${WRKSRC}/arch/arm/dts/sun8i-v3s-licheepi-zero-lcd.dts
+ ${ECHO} 'CONFIG_DM_REGULATOR=y' >> ${WRKSRC}/configs/${UBOOT_CONFIG}
+ ${ECHO} 'CONFIG_DM_PWM=y' >> ${WRKSRC}/configs/${UBOOT_CONFIG}
+ ${ECHO} 'CONFIG_PWM_SUNXI=y' >> ${WRKSRC}/configs/${UBOOT_CONFIG}
+
+.include "../../sysutils/u-boot/u-boot-arm.mk"
+.include "../../mk/bsd.pkg.mk"
diff --git a/u-boot-licheepi-zero/PLIST b/u-boot-licheepi-zero/PLIST
new file mode 100644
index 0000000000..ac4ada1af3
--- /dev/null
+++ b/u-boot-licheepi-zero/PLIST
@@ -0,0 +1,3 @@
+@comment $NetBSD: PLIST,v 1.1 2021/04/05 12:11:47 rxg Exp $
+share/u-boot/licheepi-zero/installboot.plist
+share/u-boot/licheepi-zero/u-boot-sunxi-with-spl.bin
diff --git a/u-boot-licheepi-zero/files/installboot.plist b/u-boot-licheepi-zero/files/installboot.plist
new file mode 100644
index 0000000000..32974fabb3
--- /dev/null
+++ b/u-boot-licheepi-zero/files/installboot.plist
@@ -0,0 +1,47 @@
+<!-- $NetBSD: installboot.plist,v 1.1 2021/04/05 12:11:47 rxg Exp $ -->
+<!--
+ Copyright (c) 2021 The NetBSD Foundation, Inc.
+ All rights reserved.
+
+ This code is derived from software contributed to The NetBSD Foundation
+ by Jason R. Thorpe.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+ 1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ 2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+-->
+<plist>
+<dict>
+ <key>licheepi,licheepi-zero</key>
+ <dict>
+ <key>description</key>
+ <string>Lichee Pi Zero</string>
+ <key>u-boot-install</key>
+ <array>
+ <dict>
+ <key>file-name</key>
+ <string>u-boot-sunxi-with-spl.bin</string>
+ <key>image-offset</key>
+ <integer>8192</integer>
+ </dict>
+ </array>
+ </dict>
+</dict>
+</plist>
diff --git a/u-boot-licheepi-zero/files/sun8i-v3s-licheepi-zero-lcd-480x272.dts b/u-boot-licheepi-zero/files/sun8i-v3s-licheepi-zero-lcd-480x272.dts
new file mode 100644
index 0000000000..828e907fe9
--- /dev/null
+++ b/u-boot-licheepi-zero/files/sun8i-v3s-licheepi-zero-lcd-480x272.dts
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2018 Icenowy Zheng <icenowy%aosc.io@localhost>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR X11)
+ */
+
+/ {
+ panel: panel {
+ compatible = "qiaodian,qd43003c0-40", "simple-panel";
+ backlight = <&backlight>;
+
+ bpc = <8>;
+ width-mm = <95>;
+ height-mm = <53>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&tcon0_out_lcd>;
+ };
+ };
+
+ display-timings {
+ timing0: timing0 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+
+ hfront-porch = <8>;
+ hsync-len = <4>;
+ hback-porch = <39>;
+
+ vback-porch = <2>;
+ vsync-len = <10>;
+ vfront-porch = <4>;
+ };
+ };
+ };
+};
diff --git a/u-boot-licheepi-zero/files/sun8i-v3s-licheepi-zero-lcd-800x480.dts b/u-boot-licheepi-zero/files/sun8i-v3s-licheepi-zero-lcd-800x480.dts
new file mode 100644
index 0000000000..e9448acbab
--- /dev/null
+++ b/u-boot-licheepi-zero/files/sun8i-v3s-licheepi-zero-lcd-800x480.dts
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2018 Icenowy Zheng <icenowy%aosc.io@localhost>
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR X11)
+ */
+
+/ {
+ panel: panel {
+ compatible = "urt,umsh-8596md-t", "simple-panel";
+ backlight = <&backlight>;
+
+ bpc = <6>;
+ width-mm = <152>;
+ height-mm = <91>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&tcon0_out_lcd>;
+ };
+ };
+
+ display-timings {
+ timing0: timing0 {
+ clock-frequency = <33000000>;
+ hactive = <800>;
+ vactive = <480>;
+
+ hfront-porch = <209>;
+ hsync-len = <30>;
+ hback-porch = <16>;
+
+ vback-porch = <22>;
+ vsync-len = <1>;
+ vfront-porch = <22>;
+
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
diff --git a/u-boot-licheepi-zero/patches/patch-arch_arm_dts_sun8i-v3s-licheepi-zero.dts b/u-boot-licheepi-zero/patches/patch-arch_arm_dts_sun8i-v3s-licheepi-zero.dts
new file mode 100644
index 0000000000..fad5cfc16a
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-arch_arm_dts_sun8i-v3s-licheepi-zero.dts
@@ -0,0 +1,110 @@
+$NetBSD$
+
+--- arch/arm/dts/sun8i-v3s-licheepi-zero.dts.orig 2018-11-14 16:10:06.000000000 +0000
++++ arch/arm/dts/sun8i-v3s-licheepi-zero.dts
+@@ -41,6 +41,7 @@
+ */
+
+ /dts-v1/;
++#include "sun8i-v3s-licheepi-zero-lcd.dts"
+ #include "sun8i-v3s.dtsi"
+ #include "sunxi-common-regulators.dtsi"
+
+@@ -55,10 +56,87 @@
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ blue_led {
++ label = "licheepi:blue:usr";
++ gpios = <&pio 6 1 GPIO_ACTIVE_LOW>; /* PG1 */
++ };
++
++ green_led {
++ label = "licheepi:green:usr";
++ gpios = <&pio 6 0 GPIO_ACTIVE_LOW>; /* PG0 */
++ default-state = "on";
++ };
++
++ red_led {
++ label = "licheepi:red:usr";
++ gpios = <&pio 6 2 GPIO_ACTIVE_LOW>; /* PG2 */
++ };
++ };
++
++ backlight: backlight {
++ compatible = "pwm-backlight";
++ pwms = <&pwm 0 1000000 0>;
++ brightness-levels = <0 30 40 50 60 70 100>;
++ default-brightness-level = <6>;
++ enable-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
++ };
++};
++
++&pio {
++ lcd_pins: lcd-pins {
++ pins = "PE0", "PE1", "PE2", "PE3", "PE4", "PE5",
++ "PE6", "PE7", "PE8", "PE9", "PE10", "PE11",
++ "PE12", "PE13", "PE14", "PE15", "PE16", "PE17",
++ "PE18", "PE19", "PE23", "PE24";
++ function = "lcd";
++ };
++};
++
++&codec {
++ allwinner,audio-routing =
++ "Headphone", "HP",
++ "Headphone", "HPCOM",
++ "MIC1", "Mic",
++ "Mic", "HBIAS";
++ status = "okay";
++};
++
++&emac {
++ phy-handle = <&int_mii_phy>;
++ phy-mode = "mii";
++ allwinner,leds-active-low;
++ status = "okay";
++};
++
++&de {
++ status = "okay";
++};
++
++&pwm {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pwm0_pin>;
++ status = "okay";
++};
++
++&tcon0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&lcd_pins>;
++ status = "okay";
++};
++
++&tcon0_out {
++ tcon0_out_lcd: endpoint@0 {
++ reg = <0>;
++ remote-endpoint = <&panel_input>;
++ };
+ };
+
+ &mmc0 {
+- pinctrl-0 = <&mmc0_pins_a>;
++ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+ broken-cd;
+ bus-width = <4>;
+@@ -67,7 +145,7 @@
+ };
+
+ &uart0 {
+- pinctrl-0 = <&uart0_pins_a>;
++ pinctrl-0 = <&uart0_pb_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
diff --git a/u-boot-licheepi-zero/patches/patch-arch_arm_dts_sun8i-v3s.dtsi b/u-boot-licheepi-zero/patches/patch-arch_arm_dts_sun8i-v3s.dtsi
new file mode 100644
index 0000000000..c161f6decd
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-arch_arm_dts_sun8i-v3s.dtsi
@@ -0,0 +1,399 @@
+$NetBSD$
+
+--- arch/arm/dts/sun8i-v3s.dtsi.orig 2018-11-14 16:10:06.000000000 +0000
++++ arch/arm/dts/sun8i-v3s.dtsi
+@@ -44,12 +44,28 @@
+ #include <dt-bindings/reset/sun8i-v3s-ccu.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/pinctrl/sun4i-a10.h>
++#include <dt-bindings/clock/sun8i-de2.h>
+
+ / {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
++ chosen {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++
++ framebuffer-lcd {
++ compatible = "allwinner,simple-framebuffer",
++ "simple-framebuffer";
++ allwinner,pipeline = "mixer0-lcd0";
++ clocks = <&display_clocks CLK_MIXER0>,
++ <&ccu CLK_TCON0>;
++ status = "disabled";
++ };
++ };
++
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+@@ -62,6 +78,12 @@
+ };
+ };
+
++ de: display-engine {
++ compatible = "allwinner,sun8i-v3s-display-engine";
++ allwinner,pipelines = <&mixer0>;
++ status = "disabled";
++ };
++
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+@@ -96,6 +118,102 @@
+ #size-cells = <1>;
+ ranges;
+
++ display_clocks: clock@1000000 {
++ compatible = "allwinner,sun8i-v3s-de2-clk";
++ reg = <0x01000000 0x10000>;
++ clocks = <&ccu CLK_BUS_DE>,
++ <&ccu CLK_DE>;
++ clock-names = "bus",
++ "mod";
++ resets = <&ccu RST_BUS_DE>;
++ #clock-cells = <1>;
++ #reset-cells = <1>;
++ };
++
++ mixer0: mixer@1100000 {
++ compatible = "allwinner,sun8i-v3s-de2-mixer";
++ reg = <0x01100000 0x100000>;
++ clocks = <&display_clocks 0>,
++ <&display_clocks 6>;
++ clock-names = "bus",
++ "mod";
++ resets = <&display_clocks 0>;
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ mixer0_out: port@1 {
++ reg = <1>;
++
++ mixer0_out_tcon0: endpoint {
++ remote-endpoint = <&tcon0_in_mixer0>;
++ };
++ };
++ };
++ };
++
++ syscon: system-control@1c00000 {
++ compatible = "allwinner,sun8i-v3s-system-control",
++ "allwinner,sun8i-h3-system-control";
++ reg = <0x01c00000 0xd0>;
++ #address-cells = <1>;
++ #size-cells = <1>;
++ ranges;
++ };
++
++ nmi_intc: interrupt-controller@1c000d0 {
++ compatible = "allwinner,sun8i-v3s-nmi",
++ "allwinner,sun9i-a80-nmi";
++ interrupt-controller;
++ #interrupt-cells = <2>;
++ reg = <0x01c000d0 0x0c>;
++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
++ dma: dma-controller@1c02000 {
++ compatible = "allwinner,sun8i-v3s-dma";
++ reg = <0x01c02000 0x1000>;
++ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_DMA>;
++ resets = <&ccu RST_BUS_DMA>;
++ #dma-cells = <1>;
++ };
++
++ tcon0: lcd-controller@1c0c000 {
++ compatible = "allwinner,sun8i-v3s-tcon";
++ reg = <0x01c0c000 0x1000>;
++ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_TCON0>,
++ <&ccu CLK_TCON0>;
++ clock-names = "ahb",
++ "tcon-ch0";
++ clock-output-names = "tcon-data-clock";
++ #clock-cells = <0>;
++ resets = <&ccu RST_BUS_TCON0>;
++ reset-names = "lcd";
++ status = "disabled";
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ tcon0_in: port@0 {
++ reg = <0>;
++
++ tcon0_in_mixer0: endpoint {
++ remote-endpoint = <&mixer0_out_tcon0>;
++ };
++ };
++
++ tcon0_out: port@1 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <1>;
++ };
++ };
++ };
++
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+@@ -153,6 +271,19 @@
+ #size-cells = <0>;
+ };
+
++ crypto@1c15000 {
++ compatible = "allwinner,sun8i-v3s-crypto",
++ "allwinner,sun8i-a33-crypto";
++ reg = <0x01c15000 0x1000>;
++ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
++ clock-names = "ahb", "mod";
++ dmas = <&dma 16>, <&dma 16>;
++ dma-names = "rx", "tx";
++ resets = <&ccu RST_BUS_CE>;
++ reset-names = "ahb";
++ };
++
+ usb_otg: usb@01c19000 {
+ compatible = "allwinner,sun8i-h3-musb";
+ reg = <0x01c19000 0x0400>;
+@@ -180,6 +311,29 @@
+ #phy-cells = <1>;
+ };
+
++ ehci: usb@1c1a000 {
++ compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
++ reg = <0x01c1a000 0x100>;
++ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
++ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
++ phys = <&usbphy 0>;
++ phy-names = "usb";
++ status = "disabled";
++ };
++
++ ohci: usb@1c1a400 {
++ compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
++ reg = <0x01c1a400 0x100>;
++ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
++ <&ccu CLK_USB_OHCI0>;
++ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
++ phys = <&usbphy 0>;
++ phy-names = "usb";
++ status = "disabled";
++ };
++
+ ccu: clock@01c20000 {
+ compatible = "allwinner,sun8i-v3s-ccu";
+ reg = <0x01c20000 0x400>;
+@@ -208,19 +362,46 @@
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+- uart0_pins_a: uart0@0 {
++ i2c0_pins: i2c0-pins {
++ pins = "PB6", "PB7";
++ function = "i2c0";
++ };
++
++ uart0_pb_pins: uart0-pb-pins {
+ pins = "PB8", "PB9";
+ function = "uart0";
+- bias-pull-up;
+ };
+
+- mmc0_pins_a: mmc0@0 {
++ uart2_pins: uart2-pins {
++ pins = "PB0", "PB1";
++ function = "uart2";
++ };
++
++ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3",
+ "PF4", "PF5";
+ function = "mmc0";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
++
++ mmc1_pins: mmc1-pins {
++ pins = "PG0", "PG1", "PG2", "PG3",
++ "PG4", "PG5";
++ function = "mmc1";
++ drive-strength = <30>;
++ bias-pull-up;
++ };
++
++ pwm0_pin: pwm0-pin {
++ pins = "PB4";
++ function = "pwm0";
++ };
++
++ spi0_pins: spi0-pins {
++ pins = "PC0", "PC1", "PC2", "PC3";
++ function = "spi0";
++ };
+ };
+
+ timer@01c20c00 {
+@@ -237,6 +418,41 @@
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
++ pwm: pwm@1c21400 {
++ compatible = "allwinner,sun8i-v3s-pwm",
++ "allwinner,sun7i-a20-pwm";
++ reg = <0x01c21400 0xc>;
++ clocks = <&osc24M>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
++ lradc: lradc@1c22800 {
++ compatible = "allwinner,sun4i-a10-lradc-keys";
++ reg = <0x01c22800 0x400>;
++ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++ status = "disabled";
++ };
++
++ codec: codec@1c22c00 {
++ #sound-dai-cells = <0>;
++ compatible = "allwinner,sun8i-v3s-codec";
++ reg = <0x01c22c00 0x400>;
++ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
++ clock-names = "apb", "codec";
++ resets = <&ccu RST_BUS_CODEC>;
++ dmas = <&dma 15>, <&dma 15>;
++ dma-names = "rx", "tx";
++ allwinner,codec-analog-controls = <&codec_analog>;
++ status = "disabled";
++ };
++
++ codec_analog: codec-analog@1c23000 {
++ compatible = "allwinner,sun8i-v3s-codec-analog";
++ reg = <0x01c23000 0x4>;
++ };
++
+ uart0: serial@01c28000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x01c28000 0x400>;
+@@ -270,6 +486,89 @@
+ status = "disabled";
+ };
+
++ i2c0: i2c@1c2ac00 {
++ compatible = "allwinner,sun6i-a31-i2c";
++ reg = <0x01c2ac00 0x400>;
++ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_I2C0>;
++ resets = <&ccu RST_BUS_I2C0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2c0_pins>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ i2c1: i2c@1c2b000 {
++ compatible = "allwinner,sun6i-a31-i2c";
++ reg = <0x01c2b000 0x400>;
++ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_I2C1>;
++ resets = <&ccu RST_BUS_I2C1>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
++ emac: ethernet@1c30000 {
++ compatible = "allwinner,sun8i-v3s-emac";
++ syscon = <&syscon>;
++ reg = <0x01c30000 0x10000>;
++ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
++ interrupt-names = "macirq";
++ resets = <&ccu RST_BUS_EMAC>;
++ reset-names = "stmmaceth";
++ clocks = <&ccu CLK_BUS_EMAC>;
++ clock-names = "stmmaceth";
++ phy-handle = <&int_mii_phy>;
++ phy-mode = "mii";
++ status = "disabled";
++
++ mdio: mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "snps,dwmac-mdio";
++ };
++
++ mdio_mux: mdio-mux {
++ compatible = "allwinner,sun8i-h3-mdio-mux";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ mdio-parent-bus = <&mdio>;
++ /* Only one MDIO is usable at the time */
++ internal_mdio: mdio@1 {
++ compatible = "allwinner,sun8i-h3-mdio-internal";
++ reg = <1>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ int_mii_phy: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ clocks = <&ccu CLK_BUS_EPHY>;
++ resets = <&ccu RST_BUS_EPHY>;
++ };
++ };
++ };
++ };
++
++ spi0: spi@1c68000 {
++ compatible = "allwinner,sun8i-h3-spi";
++ reg = <0x01c68000 0x1000>;
++ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
++ clock-names = "ahb", "mod";
++ dmas = <&dma 23>, <&dma 23>;
++ dma-names = "rx", "tx";
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0_pins>;
++ resets = <&ccu RST_BUS_SPI0>;
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ };
++
+ gic: interrupt-controller@01c81000 {
+ compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+ reg = <0x01c81000 0x1000>,
+@@ -280,5 +579,17 @@
+ #interrupt-cells = <3>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
++
++ csi1: camera@1cb4000 {
++ compatible = "allwinner,sun8i-v3s-csi";
++ reg = <0x01cb4000 0x3000>;
++ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_CSI>,
++ <&ccu CLK_CSI1_SCLK>,
++ <&ccu CLK_DRAM_CSI>;
++ clock-names = "bus", "mod", "ram";
++ resets = <&ccu RST_BUS_CSI>;
++ status = "disabled";
++ };
+ };
+ };
diff --git a/u-boot-licheepi-zero/patches/patch-arch_arm_include_asm_arch-sunxi_clock__sun6i.h b/u-boot-licheepi-zero/patches/patch-arch_arm_include_asm_arch-sunxi_clock__sun6i.h
new file mode 100644
index 0000000000..590d368c20
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-arch_arm_include_asm_arch-sunxi_clock__sun6i.h
@@ -0,0 +1,30 @@
+$NetBSD$
+
+--- arch/arm/include/asm/arch-sunxi/clock_sun6i.h.orig 2018-11-14 16:10:06.000000000 +0000
++++ arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+@@ -329,7 +329,7 @@ struct sunxi_ccm_reg {
+ #define AHB_GATE_OFFSET_DE 12
+ #define AHB_GATE_OFFSET_HDMI 11
+ #define AHB_GATE_OFFSET_TVE 9
+-#ifndef CONFIG_SUNXI_DE2
++#if !defined(CONFIG_SUNXI_DE2) || defined(CONFIG_MACH_SUN8I_V3S)
+ #define AHB_GATE_OFFSET_LCD1 5
+ #define AHB_GATE_OFFSET_LCD0 4
+ #else
+@@ -476,7 +476,7 @@ struct sunxi_ccm_reg {
+ #define AHB_RESET_OFFSET_HDMI 11
+ #define AHB_RESET_OFFSET_HDMI2 10
+ #define AHB_RESET_OFFSET_TVE 9
+-#ifndef CONFIG_SUNXI_DE2
++#if !defined(CONFIG_SUNXI_DE2) || defined(CONFIG_MACH_SUN8I_V3S)
+ #define AHB_RESET_OFFSET_LCD1 5
+ #define AHB_RESET_OFFSET_LCD0 4
+ #else
+@@ -508,6 +508,7 @@ struct sunxi_ccm_reg {
+ /* CCM bits common to all Display Engine 2.0 clock ctrl regs */
+ #define CCM_DE2_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+ #define CCM_DE2_CTRL_PLL_MASK (3 << 24)
++#define CCM_DE2_CTRL_PLL3_V3S (0 << 24)
+ #define CCM_DE2_CTRL_PLL6_2X (0 << 24)
+ #define CCM_DE2_CTRL_PLL10 (1 << 24)
+ #define CCM_DE2_CTRL_GATE (0x1 << 31)
diff --git a/u-boot-licheepi-zero/patches/patch-arch_arm_include_asm_arch-sunxi_gpio.h b/u-boot-licheepi-zero/patches/patch-arch_arm_include_asm_arch-sunxi_gpio.h
new file mode 100644
index 0000000000..0a23a9b5e4
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-arch_arm_include_asm_arch-sunxi_gpio.h
@@ -0,0 +1,12 @@
+$NetBSD$
+
+--- arch/arm/include/asm/arch-sunxi/gpio.h.orig 2018-11-14 16:10:06.000000000 +0000
++++ arch/arm/include/asm/arch-sunxi/gpio.h
+@@ -176,6 +176,7 @@ enum sunxi_gpio_number {
+
+ #define SUN5I_GPE_SDC2 3
+ #define SUN8I_GPE_TWI2 3
++#define SUN8I_V3S_GPE_LCD 3
+
+ #define SUNXI_GPF_SDC0 2
+ #define SUNXI_GPF_UART0 4
diff --git a/u-boot-licheepi-zero/patches/patch-arch_arm_mach-sunxi_Kconfig b/u-boot-licheepi-zero/patches/patch-arch_arm_mach-sunxi_Kconfig
new file mode 100644
index 0000000000..429c594ddb
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-arch_arm_mach-sunxi_Kconfig
@@ -0,0 +1,12 @@
+$NetBSD$
+
+--- arch/arm/mach-sunxi/Kconfig.orig 2018-11-14 16:10:06.000000000 +0000
++++ arch/arm/mach-sunxi/Kconfig
+@@ -258,6 +258,7 @@ config MACH_SUN8I_V3S
+ select CPU_V7_HAS_NONSEC
+ select CPU_V7_HAS_VIRT
+ select ARCH_SUPPORT_PSCI
++ select SUNXI_DE2
+ select SUNXI_GEN_SUN6I
+ select SUNXI_DRAM_DW
+ select SUNXI_DRAM_DW_16BIT
diff --git a/u-boot-licheepi-zero/patches/patch-drivers_pwm_sunxi__pwm.c b/u-boot-licheepi-zero/patches/patch-drivers_pwm_sunxi__pwm.c
new file mode 100644
index 0000000000..39d3f33618
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-drivers_pwm_sunxi__pwm.c
@@ -0,0 +1,12 @@
+$NetBSD$
+
+--- drivers/pwm/sunxi_pwm.c.orig 2018-11-14 16:10:06.000000000 +0000
++++ drivers/pwm/sunxi_pwm.c
+@@ -170,6 +170,7 @@ static const struct pwm_ops sunxi_pwm_op
+ static const struct udevice_id sunxi_pwm_ids[] = {
+ { .compatible = "allwinner,sun5i-a13-pwm" },
+ { .compatible = "allwinner,sun50i-a64-pwm" },
++ { .compatible = "allwinner,sun7i-a20-pwm" },
+ { }
+ };
+
diff --git a/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_lcdc.c b/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_lcdc.c
new file mode 100644
index 0000000000..694095f3d5
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_lcdc.c
@@ -0,0 +1,30 @@
+$NetBSD$
+
+--- drivers/video/sunxi/lcdc.c.orig 2024-03-30 08:20:35.015098026 +0000
++++ drivers/video/sunxi/lcdc.c
+@@ -236,7 +236,7 @@ void lcdc_pll_set(struct sunxi_ccm_reg *
+ * not sync to higher frequencies.
+ */
+ for (m = min_m; m <= max_m; m++) {
+-#ifndef CONFIG_SUNXI_DE2
++#if !defined(CONFIG_SUNXI_DE2) || defined(CONFIG_MACH_SUN8I_V3S)
+ n = (m * dotclock) / 3000;
+
+ if ((n >= 9) && (n <= 127)) {
+@@ -254,7 +254,7 @@ void lcdc_pll_set(struct sunxi_ccm_reg *
+ if (!(m & 1))
+ continue;
+ #endif
+-
++#ifndef CONFIG_MACH_SUN8I_V3S
+ /* No double clock on DE2 */
+ n = (m * dotclock) / 6000;
+ if ((n >= 9) && (n <= 127)) {
+@@ -267,6 +267,7 @@ void lcdc_pll_set(struct sunxi_ccm_reg *
+ best_double = 1;
+ }
+ }
++#endif
+ }
+
+ #ifdef CONFIG_MACH_SUN6I
diff --git a/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__de2.c b/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__de2.c
new file mode 100644
index 0000000000..1683e9758c
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__de2.c
@@ -0,0 +1,66 @@
+$NetBSD$
+
+--- drivers/video/sunxi/sunxi_de2.c.orig 2024-03-30 08:20:35.015895055 +0000
++++ drivers/video/sunxi/sunxi_de2.c
+@@ -25,8 +25,13 @@ DECLARE_GLOBAL_DATA_PTR;
+
+ enum {
+ /* Maximum LCD size we support */
++#ifdef CONFIG_MACH_SUN8I_V3S
++ LCD_MAX_WIDTH = 1024,
++ LCD_MAX_HEIGHT = 1024,
++#else
+ LCD_MAX_WIDTH = 3840,
+ LCD_MAX_HEIGHT = 2160,
++#endif
+ LCD_MAX_LOG2_BPP = VIDEO_BPP32,
+ };
+
+@@ -44,11 +49,19 @@ static void sunxi_de2_composer_init(void
+ writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
+ #endif
+
++#ifdef CONFIG_MACH_SUN8I_V3S
++ clock_set_pll3(50000000);
++ /* pll3 is also used for pixelclock and speed will be recomputed */
++ /* Set DE parent to pll3 */
++ clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
++ CCM_DE2_CTRL_PLL3_V3S);
++#else
+ clock_set_pll10(432000000);
+
+ /* Set DE parent to pll10 */
+ clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
+ CCM_DE2_CTRL_PLL10);
++#endif
+
+ /* Set ahb gating to pass */
+ setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
+@@ -74,7 +87,8 @@ static void sunxi_de2_mode_set(int mux,
+ struct de_ui * const de_ui_regs =
+ (struct de_ui *)(de_mux_base +
+ SUNXI_DE2_MUX_CHAN_REGS +
+- SUNXI_DE2_MUX_CHAN_SZ * 1);
++ SUNXI_DE2_MUX_CHAN_SZ *
++ (IS_ENABLED(CONFIG_MACH_SUN8I_V3S) ? 2 : 1));
+ struct de_csc * const de_csc_regs =
+ (struct de_csc *)(de_mux_base +
+ SUNXI_DE2_MUX_DCSC_REGS);
+@@ -101,14 +115,15 @@ static void sunxi_de2_mode_set(int mux,
+ for (channel = 0; channel < 4; channel++) {
+ void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
+ SUNXI_DE2_MUX_CHAN_SZ * channel);
+- memset(ch, 0, (channel == 0) ?
++ memset(ch, 0, (channel == 0 ||
++ (IS_ENABLED(CONFIG_MACH_SUN8I_V3S) && channel == 1)) ?
+ sizeof(struct de_vi) : sizeof(struct de_ui));
+ }
+ memset(de_bld_regs, 0, sizeof(struct de_bld));
+
+ writel(0x00000101, &de_bld_regs->fcolor_ctl);
+
+- writel(1, &de_bld_regs->route);
++ writel(IS_ENABLED(CONFIG_MACH_SUN8I_V3S) ? 2 : 1, &de_bld_regs->route);
+
+ writel(0, &de_bld_regs->premultiply);
+ writel(0xff000000, &de_bld_regs->bkcolor);
diff --git a/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__dw__hdmi.c b/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__dw__hdmi.c
new file mode 100644
index 0000000000..d04ab5419a
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__dw__hdmi.c
@@ -0,0 +1,13 @@
+$NetBSD$
+
+--- drivers/video/sunxi/sunxi_dw_hdmi.c.orig 2024-03-30 08:20:35.016849087 +0000
++++ drivers/video/sunxi/sunxi_dw_hdmi.c
+@@ -379,6 +379,8 @@ U_BOOT_DRIVER(sunxi_dw_hdmi) = {
+ .priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
+ };
+
++#ifndef CONFIG_MACH_SUN8I_V3S
+ U_BOOT_DEVICE(sunxi_dw_hdmi) = {
+ .name = "sunxi_dw_hdmi"
+ };
++#endif
diff --git a/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__lcd.c b/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__lcd.c
new file mode 100644
index 0000000000..856586a513
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-drivers_video_sunxi_sunxi__lcd.c
@@ -0,0 +1,27 @@
+$NetBSD$
+
+--- drivers/video/sunxi/sunxi_lcd.c.orig 2024-03-30 08:20:35.017516490 +0000
++++ drivers/video/sunxi/sunxi_lcd.c
+@@ -31,6 +31,13 @@ static void sunxi_lcdc_config_pinmux(voi
+ sunxi_gpio_set_cfgpin(pin, SUNXI_GPD_LCD0);
+ sunxi_gpio_set_drv(pin, 3);
+ }
++#elif defined(CONFIG_MACH_SUN8I_V3S)
++ int pin;
++
++ for (pin = SUNXI_GPE(0); pin <= SUNXI_GPE(19); pin++)
++ sunxi_gpio_set_cfgpin(pin, SUN8I_V3S_GPE_LCD);
++ sunxi_gpio_set_cfgpin(SUNXI_GPE(23), SUN8I_V3S_GPE_LCD);
++ sunxi_gpio_set_cfgpin(SUNXI_GPE(24), SUN8I_V3S_GPE_LCD);
+ #endif
+ }
+
+@@ -144,7 +151,7 @@ U_BOOT_DRIVER(sunxi_lcd) = {
+ .priv_auto_alloc_size = sizeof(struct sunxi_lcd_priv),
+ };
+
+-#ifdef CONFIG_MACH_SUN50I
++#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUN8I_V3S)
+ U_BOOT_DEVICE(sunxi_lcd) = {
+ .name = "sunxi_lcd"
+ };
diff --git a/u-boot-licheepi-zero/patches/patch-include_configs_sunxi-common.h b/u-boot-licheepi-zero/patches/patch-include_configs_sunxi-common.h
new file mode 100644
index 0000000000..ba47540128
--- /dev/null
+++ b/u-boot-licheepi-zero/patches/patch-include_configs_sunxi-common.h
@@ -0,0 +1,16 @@
+$NetBSD$
+
+--- include/configs/sunxi-common.h.orig 2024-08-31 05:16:31.758892211 +0000
++++ include/configs/sunxi-common.h
+@@ -275,7 +275,11 @@ extern int soft_i2c_gpio_scl;
+ * The amount of RAM to keep free at the top of RAM when relocating u-boot,
+ * to use as framebuffer. This must be a multiple of 4096.
+ */
++#ifdef CONFIG_MACH_SUN8I_V3S
++#define CONFIG_SUNXI_MAX_FB_SIZE (4 << 20)
++#else
+ #define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20)
++#endif
+
+ #define CONFIG_VIDEO_LOGO
+ #define CONFIG_VIDEO_STD_TIMINGS
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