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gdb-git: Enable all backends and apply commit from review
Module Name: pkgsrc-wip
Committed By: Kamil Rytarowski <n54%gmx.com@localhost>
Pushed By: kamil
Date: Wed Sep 6 16:56:52 2017 +0200
Changeset: 93bf4cebd144cc1efe43df1dfac9b0204a2754cc
Modified Files:
gdb-git/Makefile
gdb-git/distinfo
gdb-git/patches/patch-bfd_elf32-nds32.c
gdb-git/patches/patch-include_opcode_nds32.h
gdb-git/patches/patch-opcodes_nds32-asm.c
gdb-git/patches/patch-opcodes_nds32-asm.h
gdb-git/patches/patch-opcodes_nds32-dis.c
Added Files:
gdb-git/patches/patch-include_ChangeLog
gdb-git/patches/patch-opcodes_ChangeLog
Log Message:
gdb-git: Enable all backends and apply commit from review
To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=93bf4cebd144cc1efe43df1dfac9b0204a2754cc
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
diffstat:
gdb-git/Makefile | 1 +
gdb-git/distinfo | 12 +++--
gdb-git/patches/patch-bfd_elf32-nds32.c | 26 +++++-----
gdb-git/patches/patch-include_ChangeLog | 12 +++++
gdb-git/patches/patch-include_opcode_nds32.h | 4 +-
gdb-git/patches/patch-opcodes_ChangeLog | 14 ++++++
gdb-git/patches/patch-opcodes_nds32-asm.c | 72 ++++++++++++++--------------
gdb-git/patches/patch-opcodes_nds32-asm.h | 2 +-
gdb-git/patches/patch-opcodes_nds32-dis.c | 6 +--
9 files changed, 89 insertions(+), 60 deletions(-)
diffs:
diff --git a/gdb-git/Makefile b/gdb-git/Makefile
index 72706ea559..8fb037101e 100644
--- a/gdb-git/Makefile
+++ b/gdb-git/Makefile
@@ -31,6 +31,7 @@ CONFIGURE_ARGS+= --disable-gprof
CONFIGURE_ARGS+= --disable-gold
CONFIGURE_ARGS+= --disable-gas
CONFIGURE_ARGS+= --disable-ld
+CONFIGURE_ARGS+= --enable-targets=all
# In gdb/configure, depcomp is parsed with sed.
SUBST_CLASSES+= fix-depcomp
diff --git a/gdb-git/distinfo b/gdb-git/distinfo
index d23193bf23..42b2e366ef 100644
--- a/gdb-git/distinfo
+++ b/gdb-git/distinfo
@@ -3,11 +3,13 @@ $NetBSD: distinfo,v 1.10 2015/03/15 14:22:19 bsiegert Exp $
SHA1 (gdb-7.9.tar.gz) = 8f89aa6847dc87de2f720779a87ba360bdbc7efd
RMD160 (gdb-7.9.tar.gz) = 939dda771a073e82e7d72fd584246f3d1d8e9bdc
Size (gdb-7.9.tar.gz) = 33225783 bytes
-SHA1 (patch-bfd_elf32-nds32.c) = badc5e2f6de0f2d7066d6213e09aa288ea1e4bc1
+SHA1 (patch-bfd_elf32-nds32.c) = 9e624b8c833ab999876926063aaf70905254fff8
SHA1 (patch-gdb_Makefile.in) = bb23badbe730a750143f44bbd1c2cd9db9948381
SHA1 (patch-gdb_config_djgpp_djconfig.sh) = 38dd7868eaac20170b96664e0caec1cad86b8b4d
SHA1 (patch-gdb_configure.nat) = 024f2a503380b9a2f0d0914b860b1aba84d175bd
-SHA1 (patch-include_opcode_nds32.h) = f3447eb607439c26fc7fb307306d9f4fa28d0008
-SHA1 (patch-opcodes_nds32-asm.c) = 0fbefda0b00f58c44a8e46b818b5c5220bedfca9
-SHA1 (patch-opcodes_nds32-asm.h) = 2ef1b0423d57e34c622d7b9726658dd72f9941eb
-SHA1 (patch-opcodes_nds32-dis.c) = a89f8447fb973c737af4df1f7676216912815dfa
+SHA1 (patch-include_ChangeLog) = bff8af9dce12ab5d6905a185838475b8abc65f2e
+SHA1 (patch-include_opcode_nds32.h) = be07b02fe3f987aee2d35706d10c09905966c235
+SHA1 (patch-opcodes_ChangeLog) = 7445df9363f61f2fa15aaa7c603dc524dbfbab85
+SHA1 (patch-opcodes_nds32-asm.c) = e8cd4abff1fa9e945eeccd5088851495adc4250b
+SHA1 (patch-opcodes_nds32-asm.h) = 339ef4d6069389e921f10802810bbef8e45ef85e
+SHA1 (patch-opcodes_nds32-dis.c) = a0e61c139e1ba02a6dfd143bffce0fc5660ac1da
diff --git a/gdb-git/patches/patch-bfd_elf32-nds32.c b/gdb-git/patches/patch-bfd_elf32-nds32.c
index 7a69580b26..efe37f6bc1 100644
--- a/gdb-git/patches/patch-bfd_elf32-nds32.c
+++ b/gdb-git/patches/patch-bfd_elf32-nds32.c
@@ -7,7 +7,7 @@ $NetBSD$
goto done;
- if ((insn & __BIT (14)) == 0)
-+ if ((insn & __ONEBIT (14)) == 0)
++ if ((insn & N32_BIT (14)) == 0)
{
/* N32_BR1_BEQ */
if (N32_IS_RT3 (insn) && N32_RA5 (insn) == REG_R5
@@ -16,7 +16,7 @@ $NetBSD$
case N32_OP6_JI:
- if ((insn & __BIT (24)) == 0)
-+ if ((insn & __ONEBIT (24)) == 0)
++ if ((insn & N32_BIT (24)) == 0)
{
/* N32_JI_J */
if (IS_WITHIN_S (N32_IMM24S (insn), 8))
@@ -25,7 +25,7 @@ $NetBSD$
goto done;
case 0x34: /* beqzs8, bnezs8 */
- if (insn16 & __BIT (8))
-+ if (insn16 & __ONEBIT (8))
++ if (insn16 & N32_BIT (8))
insn = N32_BR2 (BNEZ, REG_TA, N16_IMM8S (insn16));
else
insn = N32_BR2 (BEQZ, REG_TA, N16_IMM8S (insn16));
@@ -34,7 +34,7 @@ $NetBSD$
{
case 0x7: /* lwi37.fp/swi37.fp */
- if (insn16 & __BIT (7)) /* swi37.fp */
-+ if (insn16 & __ONEBIT (7)) /* swi37.fp */
++ if (insn16 & N32_BIT (7)) /* swi37.fp */
insn = N32_TYPE2 (SWI, N16_RT38 (insn16), REG_FP, N16_IMM7U (insn16));
else /* lwi37.fp */
insn = N32_TYPE2 (LWI, N16_RT38 (insn16), REG_FP, N16_IMM7U (insn16));
@@ -43,7 +43,7 @@ $NetBSD$
case N32_OP6_LBSI:
/* lbsi.gp */
- oinsn = N32_TYPE1 (LBGP, N32_RT5 (insn), __BIT (19));
-+ oinsn = N32_TYPE1 (LBGP, N32_RT5 (insn), __ONEBIT (19));
++ oinsn = N32_TYPE1 (LBGP, N32_RT5 (insn), N32_BIT (19));
break;
case N32_OP6_SBI:
/* sbi.gp */
@@ -52,7 +52,7 @@ $NetBSD$
case N32_OP6_ORI:
/* addi.gp */
- oinsn = N32_TYPE1 (SBGP, N32_RT5 (insn), __BIT (19));
-+ oinsn = N32_TYPE1 (SBGP, N32_RT5 (insn), __ONEBIT (19));
++ oinsn = N32_TYPE1 (SBGP, N32_RT5 (insn), N32_BIT (19));
break;
}
break;
@@ -61,12 +61,12 @@ $NetBSD$
case N32_OP6_LHSI:
/* lhsi.gp */
- oinsn = N32_TYPE1 (HWGP, N32_RT5 (insn), __BIT (18));
-+ oinsn = N32_TYPE1 (HWGP, N32_RT5 (insn), __ONEBIT (18));
++ oinsn = N32_TYPE1 (HWGP, N32_RT5 (insn), N32_BIT (18));
break;
case N32_OP6_SHI:
/* shi.gp */
- oinsn = N32_TYPE1 (HWGP, N32_RT5 (insn), __BIT (19));
-+ oinsn = N32_TYPE1 (HWGP, N32_RT5 (insn), __ONEBIT (19));
++ oinsn = N32_TYPE1 (HWGP, N32_RT5 (insn), N32_BIT (19));
break;
}
break;
@@ -75,7 +75,7 @@ $NetBSD$
R_NDS32_PLT_GOTREL_LO19);
/* addi.gp */
- insn = N32_TYPE1 (SBGP, N32_RT5 (insn), __BIT (19));
-+ insn = N32_TYPE1 (SBGP, N32_RT5 (insn), __ONEBIT (19));
++ insn = N32_TYPE1 (SBGP, N32_RT5 (insn), N32_BIT (19));
}
else if (N32_OP6 (insn) == N32_OP6_JREG
&& N32_SUB5 (insn) == N32_JREG_JRAL)
@@ -84,13 +84,13 @@ $NetBSD$
break;
case (N32_OP6_MEM << 8) | N32_MEM_LHS:
- insn = N32_TYPE1 (HWGP, N32_RT5 (insn), __BIT (18));
-+ insn = N32_TYPE1 (HWGP, N32_RT5 (insn), __ONEBIT (18));
++ insn = N32_TYPE1 (HWGP, N32_RT5 (insn), N32_BIT (18));
irel->r_info =
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA18S1_RELA);
break;
case (N32_OP6_MEM << 8) | N32_MEM_SH:
- insn = N32_TYPE1 (HWGP, N32_RT5 (insn), __BIT (19));
-+ insn = N32_TYPE1 (HWGP, N32_RT5 (insn), __ONEBIT (19));
++ insn = N32_TYPE1 (HWGP, N32_RT5 (insn), N32_BIT (19));
irel->r_info =
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA18S1_RELA);
break;
@@ -99,7 +99,7 @@ $NetBSD$
break;
case (N32_OP6_MEM << 8) | N32_MEM_LBS:
- insn = N32_TYPE1 (LBGP, N32_RT5 (insn), __BIT (19));
-+ insn = N32_TYPE1 (LBGP, N32_RT5 (insn), __ONEBIT (19));
++ insn = N32_TYPE1 (LBGP, N32_RT5 (insn), N32_BIT (19));
irel->r_info =
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA19S0_RELA);
break;
@@ -108,7 +108,7 @@ $NetBSD$
break;
case (N32_OP6_ALU1 << 8) | N32_ALU1_ADD:
- insn = N32_TYPE1 (SBGP, N32_RT5 (insn), __BIT (19));
-+ insn = N32_TYPE1 (SBGP, N32_RT5 (insn), __ONEBIT (19));
++ insn = N32_TYPE1 (SBGP, N32_RT5 (insn), N32_BIT (19));
irel->r_info =
ELF32_R_INFO (ELF32_R_SYM (irel->r_info), R_NDS32_SDA19S0_RELA);
break;
diff --git a/gdb-git/patches/patch-include_ChangeLog b/gdb-git/patches/patch-include_ChangeLog
new file mode 100644
index 0000000000..2e0cefeb06
--- /dev/null
+++ b/gdb-git/patches/patch-include_ChangeLog
@@ -0,0 +1,12 @@
+$NetBSD$
+
+--- include/ChangeLog.orig 2017-09-05 11:19:34.000000000 +0000
++++ include/ChangeLog
+@@ -1,3 +1,7 @@
++2017-09-05 Kamil Rytarowski <n54%gmx.com@localhost>
++
++ * opcode/nds32.h: Rename __BIT() to N32_BIT().
++
+ 2017-09-05 Alexander Fedotov <alexander.fedotov%nxp.com@localhost>
+ Edmar Wienskoski <edmar.wienskoski%nxp.com@localhost
+
diff --git a/gdb-git/patches/patch-include_opcode_nds32.h b/gdb-git/patches/patch-include_opcode_nds32.h
index 5bae18607a..191b5f5f94 100644
--- a/gdb-git/patches/patch-include_opcode_nds32.h
+++ b/gdb-git/patches/patch-include_opcode_nds32.h
@@ -8,8 +8,8 @@ $NetBSD$
-#define __BIT(n) (1 << (n))
-#define __MASK(n) (__BIT (n) - 1)
-+#define __ONEBIT(n) (1 << (n))
-+#define __MASK(n) (__ONEBIT (n) - 1)
++#define N32_BIT(n) (1 << (n))
++#define __MASK(n) (N32_BIT (n) - 1)
#define __MF(v, off, bs) (((v) & __MASK (bs)) << (off))
#define __GF(v, off, bs) (((v) >> off) & __MASK (bs))
#define __SEXT(v, bs) ((((v) & ((1 << (bs)) - 1)) ^ (1 << ((bs) - 1))) - (1 << ((bs) - 1)))
diff --git a/gdb-git/patches/patch-opcodes_ChangeLog b/gdb-git/patches/patch-opcodes_ChangeLog
new file mode 100644
index 0000000000..38b7f5a5ec
--- /dev/null
+++ b/gdb-git/patches/patch-opcodes_ChangeLog
@@ -0,0 +1,14 @@
+$NetBSD$
+
+--- opcodes/ChangeLog.orig 2017-09-04 13:40:58.000000000 +0000
++++ opcodes/ChangeLog
+@@ -1,3 +1,9 @@
++2017-09-05 Kamil Rytarowski <n54%gmx.com@localhost>
++
++ * nds32-asm.c: Rename __BIT() to N32_BIT().
++ * nds32-asm.h: Likewise.
++ * nds32-dis.c: Likewise.
++
+ 2017-08-31 Nick Clifton <nickc%redhat.com@localhost>
+
+ * po/fr.po: Updated French translation.
diff --git a/gdb-git/patches/patch-opcodes_nds32-asm.c b/gdb-git/patches/patch-opcodes_nds32-asm.c
index 4f22b4e8ea..37df5967bd 100644
--- a/gdb-git/patches/patch-opcodes_nds32-asm.c
+++ b/gdb-git/patches/patch-opcodes_nds32-asm.c
@@ -8,8 +8,8 @@ $NetBSD$
-#define DEF_REG(r) (__BIT (r))
-#define USE_REG(r) (__BIT (r))
-+#define DEF_REG(r) (__ONEBIT (r))
-+#define USE_REG(r) (__ONEBIT (r))
++#define DEF_REG(r) (N32_BIT (r))
++#define USE_REG(r) (N32_BIT (r))
#define RT(r) (r << 20)
#define RA(r) (r << 15)
#define RB(r) (r << 10)
@@ -18,27 +18,27 @@ $NetBSD$
/* seg-DPREFI. */
{"dprefi.w", "%dpref_st,[%ra{+%i15s2}]", OP6 (DPREFI), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
- {"dprefi.d", "%dpref_st,[%ra{+%i15s3}]", OP6 (DPREFI) | __BIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
-+ {"dprefi.d", "%dpref_st,[%ra{+%i15s3}]", OP6 (DPREFI) | __ONEBIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
++ {"dprefi.d", "%dpref_st,[%ra{+%i15s3}]", OP6 (DPREFI) | N32_BIT (24), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
/* seg-LBGP. */
{"lbi.gp", "=rt,[+%i19s]", OP6 (LBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
- {"lbsi.gp", "=rt,[+%i19s]", OP6 (LBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
-+ {"lbsi.gp", "=rt,[+%i19s]", OP6 (LBGP) | __ONEBIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
++ {"lbsi.gp", "=rt,[+%i19s]", OP6 (LBGP) | N32_BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
/* seg-LWC/0. */
{"cplwi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (LWC), 4, 0, 0, NULL, 0, NULL},
- {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (LWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
-+ {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (LWC) | __ONEBIT (12), 4, 0, 0, NULL, 0, NULL},
++ {"cplwi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (LWC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
/* seg-SWC/0. */
{"cpswi", "%cp,=cprt,[%ra{+%i12s2}]", OP6 (SWC), 4, 0, 0, NULL, 0, NULL},
- {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (SWC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
-+ {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (SWC) | __ONEBIT (12), 4, 0, 0, NULL, 0, NULL},
++ {"cpswi.bi", "%cp,=cprt,[%ra],%i12s2", OP6 (SWC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
/* seg-LDC/0. */
{"cpldi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (LDC), 4, 0, 0, NULL, 0, NULL},
- {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (LDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
-+ {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (LDC) | __ONEBIT (12), 4, 0, 0, NULL, 0, NULL},
++ {"cpldi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (LDC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
/* seg-SDC/0. */
{"cpsdi", "%cp,%cprt,[%ra{+%i12s2}]", OP6 (SDC), 4, 0, 0, NULL, 0, NULL},
- {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (SDC) | __BIT (12), 4, 0, 0, NULL, 0, NULL},
-+ {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (SDC) | __ONEBIT (12), 4, 0, 0, NULL, 0, NULL},
++ {"cpsdi.bi", "%cp,%cprt,[%ra],%i12s2", OP6 (SDC) | N32_BIT (12), 4, 0, 0, NULL, 0, NULL},
/* seg-LSMW. */
{"lmw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW), 4, ATTR_ALL, 0, NULL, 0, NULL},
{"lmwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
@@ -46,9 +46,9 @@ $NetBSD$
- {"smw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
- {"smwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA) | __BIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
- {"smwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB) | __BIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
-+ {"smw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW) | __ONEBIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
-+ {"smwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA) | __ONEBIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
-+ {"smwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB) | __ONEBIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
++ {"smw", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMW) | N32_BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
++ {"smwa", "%abdim %rt,[%ra],%re{,%enb4}", LSMW (LSMWA) | N32_BIT (5), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
++ {"smwzb", "%abm %rt,[%ra],%re{,%enb4}", LSMW (LSMWZB) | N32_BIT (5), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
/* seg-HWGP. */
{"lhi.gp", "=rt,[+%i18s1]", OP6 (HWGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
{"lhsi.gp", "=rt,[+%i18s1]", OP6 (HWGP) | (2 << 17), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
@@ -57,11 +57,11 @@ $NetBSD$
/* seg-SBGP. */
{"sbi.gp", "%rt,[+%i19s]", OP6 (SBGP), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
- {"addi.gp", "=rt,%i19s", OP6 (SBGP) | __BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
-+ {"addi.gp", "=rt,%i19s", OP6 (SBGP) | __ONEBIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
++ {"addi.gp", "=rt,%i19s", OP6 (SBGP) | N32_BIT (19), 4, ATTR (GPREL) | ATTR_V2UP, USE_REG (29), NULL, 0, NULL},
/* seg-JI. */
{"j", "%i24s1", OP6 (JI), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
- {"jal", "%i24s1", OP6 (JI) | __BIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
-+ {"jal", "%i24s1", OP6 (JI) | __ONEBIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
++ {"jal", "%i24s1", OP6 (JI) | N32_BIT (24), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
/* seg-JREG. */
{"jr", "%rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
{"jral", "%rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
@@ -70,7 +70,7 @@ $NetBSD$
/* seg-BR1. */
{"beq", "%rt,%ra,%i14s1", OP6 (BR1), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
- {"bne", "%rt,%ra,%i14s1", OP6 (BR1) | __BIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
-+ {"bne", "%rt,%ra,%i14s1", OP6 (BR1) | __ONEBIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
++ {"bne", "%rt,%ra,%i14s1", OP6 (BR1) | N32_BIT (14), 4, ATTR_PCREL | ATTR_ALL, 0, NULL, 0, NULL},
/* seg-BR2. */
#define BR2(sub) (OP6 (BR2) | (N32_BR2_ ## sub << 16))
{"ifcall", "%i16s1", BR2 (IFCALL), 4, ATTR (IFC_EXT), 0, NULL, 0, NULL},
@@ -79,7 +79,7 @@ $NetBSD$
/* seg-BR3. */
{"beqc", "%rt,%i11br3,%i8s1", OP6 (BR3), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
- {"bnec", "%rt,%i11br3,%i8s1", OP6 (BR3) | __BIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
-+ {"bnec", "%rt,%i11br3,%i8s1", OP6 (BR3) | __ONEBIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
++ {"bnec", "%rt,%i11br3,%i8s1", OP6 (BR3) | N32_BIT (19), 4, ATTR_PCREL | ATTR_V3MUP, 0, NULL, 0, NULL},
/* seg-SIMD. */
{"pbsad", "%rt,%ra,%rb", SIMD (PBSAD), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
{"pbsada", "%rt,%ra,%rb", SIMD (PBSADA), 4, ATTR (PERF2_EXT), 0, NULL, 0, NULL},
@@ -88,27 +88,27 @@ $NetBSD$
/* seg-ALU2_FFBI. */
{"ffb", "=rt,%ra,%rb", ALU2 (FFB), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
- {"ffbi", "=rt,%ra,%ib8u", ALU2 (FFBI) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
-+ {"ffbi", "=rt,%ra,%ib8u", ALU2 (FFBI) | __ONEBIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
++ {"ffbi", "=rt,%ra,%ib8u", ALU2 (FFBI) | N32_BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
/* seg-ALU2_FLMISM. */
{"ffmism", "=rt,%ra,%rb", ALU2 (FFMISM), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
- {"flmism", "=rt,%ra,%rb", ALU2 (FLMISM) | __BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
-+ {"flmism", "=rt,%ra,%rb", ALU2 (FLMISM) | __ONEBIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
++ {"flmism", "=rt,%ra,%rb", ALU2 (FLMISM) | N32_BIT (6), 4, ATTR (STR_EXT), 0, NULL, 0, NULL},
/* seg-ALU2_MULSR64. */
{"mults64", "=dt,%ra,%rb", ALU2 (MULTS64), 4, ATTR_ALL, 0, NULL, 0, NULL},
- {"mulsr64", "=rt,%ra,%rb", ALU2 (MULSR64)| __BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
-+ {"mulsr64", "=rt,%ra,%rb", ALU2 (MULSR64)| __ONEBIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
++ {"mulsr64", "=rt,%ra,%rb", ALU2 (MULSR64)| N32_BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
/* seg-ALU2_MULR64. */
{"mult64", "=dt,%ra,%rb", ALU2 (MULT64), 4, ATTR_ALL, 0, NULL, 0, NULL},
- {"mulr64", "=rt,%ra,%rb", ALU2 (MULR64) | __BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
-+ {"mulr64", "=rt,%ra,%rb", ALU2 (MULR64) | __ONEBIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
++ {"mulr64", "=rt,%ra,%rb", ALU2 (MULR64) | N32_BIT (6), 4, ATTR_V3MEX_V2, 0, NULL, 0, NULL},
/* seg-ALU2_MADDR32. */
{"madd32", "=dt,%ra,%rb", ALU2 (MADD32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
- {"maddr32", "=rt,%ra,%rb", ALU2 (MADDR32) | __BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
-+ {"maddr32", "=rt,%ra,%rb", ALU2 (MADDR32) | __ONEBIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
++ {"maddr32", "=rt,%ra,%rb", ALU2 (MADDR32) | N32_BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
/* seg-ALU2_MSUBR32. */
{"msub32", "=dt,%ra,%rb", ALU2 (MSUB32), 4, ATTR (MAC) | ATTR (DXREG) | ATTR_ALL, 0, NULL, 0, NULL},
- {"msubr32", "=rt,%ra,%rb", ALU2 (MSUBR32) | __BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
-+ {"msubr32", "=rt,%ra,%rb", ALU2 (MSUBR32) | __ONEBIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
++ {"msubr32", "=rt,%ra,%rb", ALU2 (MSUBR32) | N32_BIT (6), 4, ATTR (MAC) | ATTR_V2UP, 0, NULL, 0, NULL},
/* seg-MISC. */
{"standby", "%stdby_st", MISC (STANDBY), 4, ATTR_ALL, 0, NULL, 0, NULL},
@@ -118,13 +118,13 @@ $NetBSD$
/* seg-MISC_SETEND. */
- {"setend.l", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
- {"setend.b", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (5) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
-+ {"setend.l", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __ONEBIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
-+ {"setend.b", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __ONEBIT (5) | __ONEBIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
++ {"setend.l", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (5), 4, ATTR_ALL, 0, NULL, 0, NULL},
++ {"setend.b", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (5) | N32_BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
/* seg-MISC_SETGIE. */
- {"setgie.d", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL},
- {"setgie.e", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __BIT (6) | __BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
-+ {"setgie.d", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __ONEBIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL},
-+ {"setgie.e", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | __ONEBIT (6) | __ONEBIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
++ {"setgie.d", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (6), 4, ATTR_ALL, 0, NULL, 0, NULL},
++ {"setgie.e", "", MISC (MTSR) | (SRIDX (1, 0, 0) << 10) | N32_BIT (6) | N32_BIT (20), 4, ATTR_ALL, 0, NULL, 0, NULL},
{"mfsr", "=rt,%ridx", MISC (MFSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
{"mtsr", "%rt,%ridx", MISC (MTSR), 4, ATTR_ALL, 0, NULL, 0, NULL},
{"trap", "", MISC (TRAP), 4, ATTR_V3MEX_V1, 0, NULL, 0, NULL},
@@ -134,8 +134,8 @@ $NetBSD$
{"ksubw", "=rt,%ra,%rb", ALU2 (KSUB), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"kaddh", "=rt,%ra,%rb", ALU2 (KADD) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"ksubh", "=rt,%ra,%rb", ALU2 (KSUB) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"kaddh", "=rt,%ra,%rb", ALU2 (KADD) | __ONEBIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"ksubh", "=rt,%ra,%rb", ALU2 (KSUB) | __ONEBIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"kaddh", "=rt,%ra,%rb", ALU2 (KADD) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"ksubh", "=rt,%ra,%rb", ALU2 (KSUB) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
{"kdmbb", "=rt,%ra,%rb", ALU2 (KMxy), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"kdmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"kdmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
@@ -144,18 +144,18 @@ $NetBSD$
- {"khmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"khmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"khmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __BIT (8) | __BIT (6) | __BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"kdmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"kdmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"kdmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (6) | __ONEBIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"khmbb", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (8), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"khmbt", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (8) | __ONEBIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"khmtb", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (8) | __ONEBIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"khmtt", "=rt,%ra,%rb", ALU2 (KMxy) | __ONEBIT (8) | __ONEBIT (6) | __ONEBIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"kdmbt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"kdmtb", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"kdmtt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (6) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"khmbb", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"khmbt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8) | N32_BIT (6), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"khmtb", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"khmtt", "=rt,%ra,%rb", ALU2 (KMxy) | N32_BIT (8) | N32_BIT (6) | N32_BIT (7), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
{"kslraw", "=rt,%ra,%rb", ALU2 (KSLRA), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"rdov", "=rt", ALU2 (MFUSR) | __BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
- {"clrov", "", ALU2 (MTUSR) | __BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"rdov", "=rt", ALU2 (MFUSR) | __ONEBIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
-+ {"clrov", "", ALU2 (MTUSR) | __ONEBIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"rdov", "=rt", ALU2 (MFUSR) | N32_BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
++ {"clrov", "", ALU2 (MTUSR) | N32_BIT (6) | ( 0x1e << 15), 4, ATTR (SATURATION_EXT), 0, NULL, 0, NULL},
/* Audio ext. instructions. */
diff --git a/gdb-git/patches/patch-opcodes_nds32-asm.h b/gdb-git/patches/patch-opcodes_nds32-asm.h
index 14ad8f76b4..0c68818831 100644
--- a/gdb-git/patches/patch-opcodes_nds32-asm.h
+++ b/gdb-git/patches/patch-opcodes_nds32-asm.h
@@ -7,7 +7,7 @@ $NetBSD$
#define MISC(sub) (OP6 (MISC) | N32_MISC_ ## sub)
#define MEM(sub) (OP6 (MEM) | N32_MEM_ ## sub)
-#define FPU_RA_IMMBI(sub) (OP6 (sub) | __BIT (12))
-+#define FPU_RA_IMMBI(sub) (OP6 (sub) | __ONEBIT (12))
++#define FPU_RA_IMMBI(sub) (OP6 (sub) | N32_BIT (12))
#define FS1(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_ ## sub << 6))
#define FS1_F2OP(sub) (OP6 (COP) | N32_FPU_FS1 | (N32_FPU_FS1_F2OP << 6) \
| (N32_FPU_FS1_F2OP_ ## sub << 10))
diff --git a/gdb-git/patches/patch-opcodes_nds32-dis.c b/gdb-git/patches/patch-opcodes_nds32-dis.c
index 6cf5bc755f..22268b5f7c 100644
--- a/gdb-git/patches/patch-opcodes_nds32-dis.c
+++ b/gdb-git/patches/patch-opcodes_nds32-dis.c
@@ -7,12 +7,12 @@ $NetBSD$
case N32_OP6_ALU2:
/* FFBI */
- if (__GF (insn, 0, 7) == (N32_ALU2_FFBI | __BIT (6)))
-+ if (__GF (insn, 0, 7) == (N32_ALU2_FFBI | __ONEBIT (6)))
++ if (__GF (insn, 0, 7) == (N32_ALU2_FFBI | N32_BIT (6)))
return MASK_OP (insn, 0x7f);
- else if (__GF (insn, 0, 7) == (N32_ALU2_MFUSR | __BIT (6))
- || __GF (insn, 0, 7) == (N32_ALU2_MTUSR | __BIT (6)))
-+ else if (__GF (insn, 0, 7) == (N32_ALU2_MFUSR | __ONEBIT (6))
-+ || __GF (insn, 0, 7) == (N32_ALU2_MTUSR | __ONEBIT (6)))
++ else if (__GF (insn, 0, 7) == (N32_ALU2_MFUSR | N32_BIT (6))
++ || __GF (insn, 0, 7) == (N32_ALU2_MTUSR | N32_BIT (6)))
/* RDOV CLROV */
return MASK_OP (insn, 0xf81ff);
return MASK_OP (insn, 0x1ff);
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