Import verilator-3.878 as wip/verilator.

[Kamil Rytarowski <n54%gmx.com@localhost>]

Module Name:	pkgsrc-wip
Committed By:	Kamil Rytarowski <n54%gmx.com@localhost>
Pushed By:	kamil
Date:		Sat Nov 28 22:21:14 2015 +0100
Changeset:	a7911fd42430efb9530dd8daf69cb8baec806726

Added Files:
	verilator/DESCR
	verilator/Makefile
	verilator/PLIST
	verilator/distinfo

Log Message:
Import verilator-3.878 as wip/verilator.

Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs for
embedded software design teams.

To see a diff of this commit:
https://wip.pkgsrc.org/cgi-bin/gitweb.cgi?p=pkgsrc-wip.git;a=commitdiff;h=a7911fd42430efb9530dd8daf69cb8baec806726

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

diffstat:
 verilator/DESCR    |  6 ++++++
 verilator/Makefile | 40 ++++++++++++++++++++++++++++++++++++++++
 verilator/PLIST    |  1 +
 verilator/distinfo |  5 +++++
 4 files changed, 52 insertions(+)

diffs:
diff --git a/verilator/DESCR b/verilator/DESCR
new file mode 100644
index 0000000..b3ee709
--- /dev/null
+++ b/verilator/DESCR
@@ -0,0 +1,6 @@
+Verilator is the fastest free Verilog HDL simulator, and beats most commercial
+simulators. It compiles synthesizable Verilog (not test-bench code!), plus some
+PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is
+designed for large projects where fast simulation performance is of primary
+concern, and is especially well suited to generate executable models of CPUs for
+embedded software design teams.
diff --git a/verilator/Makefile b/verilator/Makefile
new file mode 100644
index 0000000..304987f
--- /dev/null
+++ b/verilator/Makefile
@@ -0,0 +1,40 @@
+# $NetBSD$
+
+DISTNAME=	verilator-3.878
+CATEGORIES=	wip
+MASTER_SITES=	http://www.veripool.org/ftp/
+EXTRACT_SUFX=	.tgz
+
+MAINTAINER=	pkgsrc-users%NetBSD.org@localhost
+HOMEPAGE=	http://www.veripool.org/wiki/verilator/Intro
+COMMENT=	Free and fast Verilog HDL simulator
+LICENSE=	gnu-lgpl-v3 OR artistic
+
+GNU_CONFIGURE=	yes
+USE_TOOLS+=	pkg-config bison gmake perl autoconf flex
+USE_LANGUAGES=	c c++
+
+DEPENDS+=	p5-Getopt-Long>=[0-9]*:../../devel/p5-Getopt-Long
+
+REPLACE_PERL+=	test_regress/*.pl
+REPLACE_PERL+=	test_regress/t/*.pl
+REPLACE_PERL+=	test_regress/t/t_pipe_filter.pf
+REPLACE_PERL+=	test_regress/t/t_pipe_exit_bad.pf
+REPLACE_PERL+=	test_regress/t/t_case_deep.v
+REPLACE_PERL+=	src/vlcovgen
+REPLACE_PERL+=	src/bisonpre
+REPLACE_PERL+=	src/config_rev.pl
+REPLACE_PERL+=	src/cppcheck_filtered
+REPLACE_PERL+=	src/astgen
+REPLACE_PERL+=	src/pod2latexfix
+REPLACE_PERL+=	src/flexfix
+REPLACE_PERL+=	test_verilated/*.pl
+
+PKGCONFIG_OVERRIDE+=	verilator.pc.in
+
+TEST_TARGET=	test
+
+pre-configure:
+	${RUN} cd ${WRKSRC} && autoconf
+
+.include "../../mk/bsd.pkg.mk"
diff --git a/verilator/PLIST b/verilator/PLIST
new file mode 100644
index 0000000..48d96a5
--- /dev/null
+++ b/verilator/PLIST
@@ -0,0 +1 @@
+@comment $NetBSD$
diff --git a/verilator/distinfo b/verilator/distinfo
new file mode 100644
index 0000000..f92afc7
--- /dev/null
+++ b/verilator/distinfo
@@ -0,0 +1,5 @@
+$NetBSD$
+
+SHA1 (verilator-3.878.tgz) = 51d08bc91b3ad58e3eed69df78ed9d8b6e4c0cf9
+RMD160 (verilator-3.878.tgz) = 973b7599791657bc90d2f035557c71e5dacda4e6
+Size (verilator-3.878.tgz) = 1992325 bytes