CVS commit: pkgsrc/cad/MyHDL-iverilog

["Ryo ONODERA" <ryoon%netbsd.org@localhost>]

Module Name:    pkgsrc
Committed By:   ryoon
Date:           Thu Jul  4 13:07:29 UTC 2019

Modified Files:
        pkgsrc/cad/MyHDL-iverilog: DESCR

Log Message:
Add package specific description


To generate a diff of this commit:
cvs rdiff -u -r1.1.1.1 -r1.2 pkgsrc/cad/MyHDL-iverilog/DESCR

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: pkgsrc/cad/MyHDL-iverilog/DESCR
diff -u pkgsrc/cad/MyHDL-iverilog/DESCR:1.1.1.1 pkgsrc/cad/MyHDL-iverilog/DESCR:1.2
--- pkgsrc/cad/MyHDL-iverilog/DESCR:1.1.1.1     Fri Feb 10 17:05:03 2006
+++ pkgsrc/cad/MyHDL-iverilog/DESCR     Thu Jul  4 13:07:29 2019
@@ -5,3 +5,5 @@ can be viewed as a "scripting language" 
 languages. However, Python is more accurately described as a very
 high level language (VHLL). MyHDL users have access to the
 amazing power and elegance of Python for their modeling work.
+
+This package is Icarus Verilog cosimulation support for py-MyHDL.