CVS commit: pkgsrc/cad/MyHDL-iverilog

["Kamil Rytarowski" <kamil%netbsd.org@localhost>]

Module Name:    pkgsrc
Committed By:   kamil
Date:           Sat Oct  8 23:11:23 UTC 2016

Modified Files:
        pkgsrc/cad/MyHDL-iverilog: Makefile

Log Message:
Switch from cad/verilog to cad/iverilog

Bump PKGREVISION to 1.


To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 pkgsrc/cad/MyHDL-iverilog/Makefile

Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.

Modified files:

Index: pkgsrc/cad/MyHDL-iverilog/Makefile
diff -u pkgsrc/cad/MyHDL-iverilog/Makefile:1.8 pkgsrc/cad/MyHDL-iverilog/Makefile:1.9
--- pkgsrc/cad/MyHDL-iverilog/Makefile:1.8      Sun Jan  4 02:45:50 2015
+++ pkgsrc/cad/MyHDL-iverilog/Makefile  Sat Oct  8 23:11:23 2016
@@ -1,8 +1,9 @@
-# $NetBSD: Makefile,v 1.8 2015/01/04 02:45:50 mef Exp $
+# $NetBSD: Makefile,v 1.9 2016/10/08 23:11:23 kamil Exp $
 #
 
 DISTNAME=      myhdl-0.8.1
 PKGNAME=       MyHDL-iverilog-0.7
+PKGREVISION=   1
 PKGNAME=       ${DISTNAME:C/myhdl/MyHDL-iverilog/}
 CATEGORIES=    cad python
 MASTER_SITES=  ${MASTER_SITE_SOURCEFORGE:=myhdl/}
@@ -23,5 +24,5 @@ do-install:
 #do-test:
 #      (cd ${WRKSRC}/cosimulation/icarus/test && ${PYTHONBIN} test_all.py)
 
-.include "../../cad/verilog/buildlink3.mk"
+.include "../../cad/iverilog/buildlink3.mk"
 .include "../../mk/bsd.pkg.mk"